EP1SGX25DF800C6N vs EP1SGX25DF800I6N 比較
詳細並排比較 EP1SGX25DF800C6N 由 Intel 與 EP1SGX25DF800I6N 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Intel
EP1SGX25DF800C6N - Stratix GX FPGA, 25K LE, 3.1875 Gbps SERDES | Intel / Altera
EP1SGX25DF800C6N ObsoleteIntel
EP1SGX25DF800I6N - Stratix GX FPGA, 25K LE, 20x 3.1875 Gbps Transceivers | Intel / Altera
EP1SGX25DF800I6N ⚠ 最後購買機會規格比較
| 參數 | EP1SGX25DF800C6N | EP1SGX25DF800I6N |
|---|---|---|
| 品牌 | Intel | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | 最後購買 |
| Family | Stratix GX | Stratix GX |
| Logic Elements | 25,560 LEs | [DATA_NEEDED: logic element count] |
| Maximum Transceiver Channels | 20 channels | — |
| Maximum Transceiver Data Rate | 3.1875 Gbps | 3.1875 Gbps per channel |
| 封裝 | FBGA-780 (FineLine BGA, 800-ball per JEDEC ordering code) | 800-pin FineLine BGA (DF800) |
| Process Node | [DATA_NEEDED: process node] | — |
| Core Voltage | 1.5 V | — |
| 工作溫度 | Commercial (0 C to +85 C) | — |
| Speed Grade | 6 | -6 (production grade) |
| Configuration Method | Passive Serial / Passive Parallel / Active Serial / JTAG | — |
| Transceiver Encoding | 8B/10B | — |
| Clock Data Recovery (CDR) | Yes, integrated per channel | — |
| 記憶體類型 | TriMatrix embedded SRAM | — |
| DSP Blocks | Yes, embedded multiplier blocks | Up to 22 DSP blocks |
| 安裝類型 | Surface Mount (BGA) | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Lead Free | [DATA_NEEDED: lead free status] | — |
| Transceiver Channels | — | 4 to 20 channels |
| CDR / SERDES | — | Embedded clock-data recovery and SERDES |
| Memory | — | TriMatrix memory, up to 2 Mbits |
| Hard IP | — | PCI Express PHY, external memory interfaces (DDR, DDR-II, QDR-II, RLDRAM-II) |
| Source-Synchronous Channels | — | 8 channels |
| I/O Standards | — | LVDS, LVTTL, LVCMOS, SSTL, HSTL |
| Temperature Range | — | Industrial -40C to +100C |
| Protocol Support | — | Gigabit Ethernet, SONET/SDH, PCI Express, custom serial |