EP2A25F672C7N vs EP2A25F672C9N 比較
詳細並排比較 EP2A25F672C7N 由 Altera 與 EP2A25F672C9N 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP2A25F672C7N | EP2A25F672C9N |
|---|---|---|
| 品牌 | Altera | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | APEX II | APEX II |
| Logic Elements | 24,320 cells | — |
| System Gates | Approximately 900,000 | Approx. 900000 |
| User I/Os | 492 | — |
| Propagation Delay (tPD) | 1.69 ns | — |
| Internal Operating Frequency | Up to 500 MHz | — |
| Core Voltage (VCCINT) | 1.5 V | — |
| Process Technology | 0.15 µm all-layer copper (up to 8 metal layers) | 0.15 µm all-layer copper, up to 8 metal layers |
| Logic Family | CMOS | CMOS |
| Package Type | 672-ball FC-FBGA (FineLine BGA) | — |
| Package Body Size | 27 x 27 mm | — |
| Ball Pitch | 1.0 mm | — |
| 工作溫度 | 0 °C to 85 °C (commercial) | 0 °C to +85 °C (commercial, C9 grade) |
| High-Speed I/O Support | True-LVDS, LVPECL, PCML, HyperTransport up to 1 Gbps | — |
| Programmable Logic Type | Loadable PLD (in-system programmable) | — |
| Embedded Memory | Embedded System Blocks (ESB) configurable as dual-port RAM/ROM | Enhanced System Blocks (ESBs) for dual-port RAM |
| PLLs | Up to 4 | — |
| 安裝類型 | Surface Mount | Surface Mount (BGA) |
| RoHS 狀態 | [DATA_NEEDED: RoHS compliance] | Compliant (per distributor listings) |
| Logic Elements / Cells | — | 24320 |
| Maximum User I/O | — | 492 |
| Operating Frequency | — | 236 MHz |
| Core Supply Voltage (VCCINT) | — | 1.425 V to 1.575 V (nominal 1.5 V) |
| 封裝 | — | 672-ball FineLine BGA (F672), 27 × 27 mm, 1.00 mm pitch |
| Seated Height (max) | — | 2.100 mm |
| Propagation Delay | — | 2.23 ns |
| I/O Standards Supported | — | LVTTL, LVCMOS, PCI, GTL+, SSTL-2/3, LVDS, LVPECL, PCML, HyperTransport |
| LVDS Data Rate | — | Up to 1 Gbps (True-LVDS) |
| Configuration Interface | — | Serial / Parallel PROM, JTAG, passive parallel (enhanced) |
| Design Software | — | Quartus II (v5.1 or later) |