EP2SGX130GF40C3NES vs EP2SGX130GF40C4NES 比較

詳細並排比較 EP2SGX130GF40C3NES 由 Altera 與 EP2SGX130GF40C4NES 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。

Altera

EP2SGX130GF40C3NES - Stratix II GX FPGA, 132K LE, 6.375Gbps | Altera

EP2SGX130GF40C3NES Obsolete

Intel

EP2SGX130GF40C4NES ⚠ 最後購買機會

參數	EP2SGX130GF40C3NES	EP2SGX130GF40C4NES
品牌	Altera	Intel
類別	FPGA & CPLD	FPGA & CPLD
生命週期狀態	Obsolete	最後購買
Family	Stratix II GX	Stratix II GX
Logic Elements	132540	132,540
Logic Array Blocks (LABs)	7047	—
Maximum Internal Frequency	778.82 MHz	—
Process Technology	90 nm CMOS	90 nm CMOS
Core Voltage	1.2 V	1.2 V
Transceiver Channels	4 to 20 (per device family configuration)	Up to 20 (4 to 20, device-dependent)
Maximum Transceiver Data Rate	6.375 Gbps	6.375 Gbps
Transceiver Feature	Embedded SERDES with Clock/Data Recovery (CRU)	—
記憶體類型	TriMatrix embedded memory (distributed RAM, block RAM, shift register)	—
封裝	1508-ball FC-FBGA (40 x 40 mm, 1 mm pitch)	—
Operating Temperature Grade	Commercial Extended	—
Terminal Form	Ball (BGA)	—
安裝類型	Surface Mount	Surface Mount (flip-chip BGA)
RoHS 狀態	Lead-free compliant (per package code MS-034AAU-1)	—
Series	EP2SGX130	—
Logic Blocks / ALMs	—	Approximately 53,000 ALMs
User I/O Pins	—	734
Total Package Pins	—	1508 (FC-FBGA ball grid)
Package Code	—	GF40 (FC-FBGA, 40x40 mm, 1.0 mm pitch)
Speed Grade	—	C4 (speed grade -4)
Internal Operating Frequency	—	Up to 717 MHz
Embedded Memory	—	Approximately 4.5 Mbits (TriMatrix)
PLL Blocks	—	8
DSP Blocks	—	Yes (variable, see datasheet)
Lead-Free / RoHS	—	Yes (LEAD FREE per datasheet family code)
MSL 等級	—	Per JEDEC J-STD-020, typically MSL-4 or higher [DATA_NEEDED: exact MSL level]
工作溫度	—	Commercial Extended (per N suffix)
JEDEC Standard Reference	—	MS-034AAU-1