EPM5032DC vs EPM5032DC-25 比較
詳細並排比較 EPM5032DC 由 Altera 與 EPM5032DC-25 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM5032DC | EPM5032DC-25 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | NRND |
| Family | MAX 5000 | — |
| Device Type | EPLD (Erasable Programmable Logic Device) | UV Erasable Programmable Logic Device (EPLD) |
| Macrocells | 32 | 32 |
| Logic Array Blocks (LABs) | 1 | — |
| 封裝 | DIP-24 (ceramic, windowed) | CDIP-28 (Windowed Ceramic DIP-28) |
| Speed Grade | DC (commercial) | — |
| 工作溫度 | 0C to +70C | [DATA_NEEDED: operating temperature range] |
| Technology | Bipolar EPROM, UV-erasable | — |
| Programmable Logic Elements | AND array + fixed OR array per macrocell | — |
| Configuration Memory | EPROM (UV-erasable via package window) | — |
| 安裝類型 | Through-hole (DIP) | — |
| 腳位數 | 24 | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS status] | Lead Free / RoHS Compliant (per distributor listings) |
| Programming Tool | Altera MAX+PLUS II / A+PLUS legacy | — |
| 生命週期狀態 | Obsolete (mature legacy) | — |
| Manufacturer | — | Altera (Intel Programmable Solutions Group) |
| Product Family | — | MAX 5000 |
| Pin-to-Pin Propagation Delay (tPD) | — | 25 ns |
| Maximum Counter Frequency (fCNT) | — | [DATA_NEEDED: maximum counter frequency] |
| Setup Time (tSU) | — | [DATA_NEEDED: setup time] |
| Number of Dedicated Inputs | — | 32 (in DIP-28 pinout) |
| Number of I/O Pins | — | 22 (in DIP-28 pinout, 4 used as dedicated inputs) |
| Process Technology | — | CMOS, EPROM (UV-Erasable) |
| Architecture | — | PAL-Type, Single-LAB, 32-Macrocell |
| Output Structure | — | Programmable I/O with output enable |
| Flip-Flop Configuration | — | D, T, JK, or SR (programmable) |
| Programming Method | — | UV erase + Altera/Intel MAX+PLUS II programmer |
| Erasure Method | — | UV light through ceramic window |