EPM5128JC-1 vs EPM5128JC 比較
詳細並排比較 EPM5128JC-1 由 Altera 與 EPM5128JC 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM5128JC-1 | EPM5128JC |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | MAX 5000 | — |
| Device Type | Erasable Programmable Logic Device (EPLD/CPLD) | EPLD / CPLD |
| Macrocells | 128 | — |
| Usable Gates | 2,500 | — |
| Logic Array Blocks (LABs) | [DATA_NEEDED: LAB count] | — |
| Maximum Operating Frequency | 62.5 MHz | — |
| Pin-to-Pin Propagation Delay (tPD) | 40 ns | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) | 5 V (typical) |
| Technology | CMOS, UV-erasable EPROM | — |
| 封裝 | 68-pin CQCCJ (Windowed Ceramic J-Lead Chip Carrier) | — |
| 安裝類型 | Surface Mount | Surface Mount (PLCC socket or solder) |
| 工作溫度 | [DATA_NEEDED: temperature grade] | Commercial 0C to +70C |
| Programming Interface | JTAG / Altera dedicated programmer | Altera MAX+PLUS II / A+PLUS / legacy programmer |
| Configuration Memory | Non-volatile EPROM (UV-erasable) | UV-erasable EPROM (windowed package) |
| RoHS 狀態 | non_compliant (ceramic windowed package) | [DATA_NEEDED: RoHS status - legacy part] |
| 生命週期狀態 | Obsolete - last-time-buy inventory only | — |
| Product Family | — | MAX 5000 |
| Macrocell Count | — | 128 |
| Propagation Delay (tPD) | — | 35 ns |
| Logic Elements | — | Programmable AND/OR/XOR array |
| 腳位數 | — | 68 |
| Package Type | — | PLCC-68 (JLCC) ceramic, J-leaded |
| Dedicated Inputs | — | 8 |
| User I/O Pins | — | [DATA_NEEDED: user I/O pin count] |
| Boundary Scan | — | JTAG IEEE 1149.1 (family feature) |
| Process Technology | — | CMOS EPROM |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |