EPM5192LC-25 vs EPM5192LC-M091A 比較
詳細並排比較 EPM5192LC-25 由 Altera 與 EPM5192LC-M091A 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM5192LC-25 | EPM5192LC-M091A |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Product Type | CPLD (Complex Programmable Logic Device) | — |
| Family | MAX 5000 | — |
| Macrocells | 192 | 192 |
| Logic Elements | 192 (1 macrocell ≈ 1 LE in MAX 5000 architecture) | — |
| Pin-to-Pin Delay (tPD) | 25 ns | — |
| Speed Grade | -25 (25 ns) | — |
| 封裝 | JLCC-84 (ceramic J-lead chip carrier) | LC (custom pin-grid / customer-specific, M091A designation) |
| 安裝類型 | Surface Mount | — |
| Programmable Technology | UV-erasable / OTP (EPROM-based) | — |
| Programming Interface | JTAG / Altera programming hardware (legacy) | — |
| 工作溫度 | 0C to +70C (commercial) | [DATA_NEEDED: operating temperature grade] |
| 供應電壓 | 5 V (typical, MAX 5000) | — |
| I/O Standard | TTL-compatible | — |
| Configuration Memory | Non-volatile EPROM (on-chip) | Non-volatile EPROM (UV-erasable) |
| Manufacturer | Altera Corporation (now Intel PSG) | — |
| RoHS 狀態 | Unknown (legacy ceramic package typically non-RoHS) | [DATA_NEEDED: RoHS status for EPM5192LC-M091A] |
| Device Family | — | MAX 5000 EPLD |
| User I/O Pins | — | 64 |
| Dedicated Inputs | — | 7 |
| Logic Array Blocks (LABs) | — | 12 |
| Global Clock Inputs | — | 1 |
| Propagation Delay (tpd) | — | 55 ns (typical, MAX 5000 family) |
| Supply Voltage (Vcc) | — | 5 V |
| Technology | — | UV-erasable CMOS, EPROM-based |
| Interconnect | — | Programmable Interconnect Array (PIA) |
| 腳位數 | — | [DATA_NEEDED: pin count of LC-M091A package] |
| Development Tool | — | Altera MAX+PLUS II (legacy) |