EPM5192LC-2N vs EPM5192JC-2 比較
詳細並排比較 EPM5192LC-2N 由 Altera 與 EPM5192JC-2 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM5192LC-2N | EPM5192JC-2 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | MAX 5000 | — |
| Macrocells | 192 | 192 |
| Flip-Flops | 192 | — |
| Logic Elements | 192 macrocells (PAL/GAL-style AND-OR array) | — |
| Package Type | LC (ceramic J-leaded, windowed UV-erasable package family) | — |
| Speed Grade | -2 (tPD approximately 25 ns) | — |
| Propagation Delay (typical) | 25 ns | — |
| 供應電壓 | 5 V (typical) | — |
| Programmability | UV-erasable EPROM cell | — |
| 安裝類型 | Surface Mount (LC package) | Surface Mount |
| 工作溫度 | Commercial (0C to +70C) - inferred from speed-grade -2 designation | — |
| RoHS 狀態 | Compliant (per -N lead-free suffix) | [DATA_NEEDED: RoHS compliance] |
| Lead-Free | Yes (per -N suffix) | — |
| Architecture | Programmable Logic Array (PLA) with global PIA | — |
| Programming Interface | Altera programming hardware (MAX+PLUS II / ByteBlaster compatible) | — |
| Device Family | — | MAX 5000 |
| Product Type | — | UV-erasable Programmable Logic Device (PLD) |
| Logic Array Blocks (LABs) | — | 12 |
| Interconnect | — | Programmable Interconnect Array (PIA) |
| User I/O Pins | — | 64 |
| Dedicated Inputs | — | 7 |
| External Clock Inputs | — | 1 |
| Propagation Delay (tPD) | — | 45 ns |
| 最大時脈頻率 | — | 40 MHz |
| Process Technology | — | CMOS |
| 封裝 | — | 84-pin CQCC (Ceramic Quad Flat Pack, J-lead, windowed) |
| Number of Terminals | — | 84 |
| Programming Method | — | UV-erase / EPROM |
| 工作溫度範圍 | — | [DATA_NEEDED: operating temperature range] |