EPM9320ALC84-15 vs EPM9320ALC84-20 比較
詳細並排比較 EPM9320ALC84-15 由 Altera 與 EPM9320ALC84-20 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM9320ALC84-15 | EPM9320ALC84-20 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | NRND | NRND |
| Family | MAX 9000 CPLD | MAX 9000 |
| Macrocells | 320 | 320 |
| Usable Gates | 6000 | — |
| Propagation Delay (tPD) | 16 ns | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) | — |
| User I/O | 56 | — |
| Logic Array Blocks (LABs) | 16 | 16 |
| Technology | CMOS, EEPROM-based configuration | — |
| 封裝 | 84-pin PLCC (S-PQCC-J84, J-lead) | PLCC-84 |
| 安裝類型 | Through-hole / socket | Surface Mount (PLCC socket compatible) |
| Programming Interface | JTAG (IEEE 1149.1) / ISP | — |
| 工作溫度 | -40C to +85C (industrial) | [DATA_NEEDED: commercial or industrial grade] |
| RoHS 狀態 | [DATA_NEEDED: rohs status] | [DATA_NEEDED: per Altera datasheet] |
| 濕度敏感等級 (MSL) | MSL-3 (168 hours per fpgalink.com) | — |
| Lead-Free / Halogen-Free | [DATA_NEEDED: lead free status] | — |
| RoHS3 Compliance | ROHS3 Compliant (per fpgalink.com listing) | — |
| Device Type | — | EPLD (Erasable Programmable Logic Device) |
| Maximum User I/Os | — | 212 |
| Pin-to-Pin Delay (tPD) | — | 20 ns |
| Process Technology | — | 0.5 µm CMOS EEPROM |
| 供應電壓 | — | 5.0 V |
| Programmability | — | In-system via IEEE 1149.1 JTAG |
| Configuration Memory | — | Non-volatile EEPROM |
| Boundary Scan | — | JTAG IEEE 1149.1 |
| Design Software | — | MAX+PLUS II / Quartus II (legacy) |