SN65LVDS105PWR vs TD1205 比較
詳細並排比較 SN65LVDS105PWR 由 Texas Instruments 與 TD1205 由 TD next. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | SN65LVDS105PWR | TD1205 |
|---|---|---|
| 品牌 | Texas Instruments | TD next |
| 類別 | Clock & Timing | RF Modules |
| 生命週期狀態 | 啟用中 | 啟用中 |
| 功能 | 1 LVTTL input to 4 LVDS output repeater / fanout buffer | — |
| 資料速率 | 400 Mbps | — |
| Max Clock Frequency | 400 MHz | — |
| 供應電壓 | 3 V to 3.6 V (typical 3.3 V) | [DATA_NEEDED: VBAT operating range] |
| Input Type | LVTTL (single-ended) | — |
| 輸出類型 | LVDS (differential), 4 pairs | — |
| Output Voltage (typical) | 350 mV into 100 ohm load | — |
| Standard Compliance | ANSI EIA/TIA-644 LVDS | — |
| 通道數 | 1 x 1:4 | — |
| 封裝 | 16-TSSOP (PW) | — |
| 安裝類型 | Surface Mount | Surface Mount (reflow) |
| Technology | LVDS differential signaling | — |
| 類別 | Signal Buffers, Repeaters, Splitters - Clock Buffer | — |
| 工作溫度 | [DATA_NEEDED: operating temperature range] | -40C to +85C |
| 靜態電流 | [DATA_NEEDED: quiescent current] | — |
| Input Rise/Fall Time Note | TTL/CMOS rise/fall < 500 ps may require low-Dk laminate per TI layout guidance | — |
| Product Type | — | Sigfox-certified RF transceiver module |
| Manufacturer | — | TD next (Telecom Design) |
| RF Protocol | — | Sigfox (Ultra-Narrow-Band LPWAN) |
| Operating Frequency (RC1) | — | 868 MHz (ETSI Europe) |
| Operating Frequency (RC2) | — | 902-928 MHz (US, Australia, Japan) |
| Tx Power (RC1) | — | +14 dBm typical |
| Tx Power (RC2) | — | +22 dBm maximum |
| Receiver Sensitivity | — | [DATA_NEEDED: receiver sensitivity] |
| Integrated Microcontroller | — | ARM Cortex-M0+ (STM32 family) |
| Clock Reference | — | Integrated TCXO |
| Host Interface | — | UART, SPI, I2C, GPIO |
| Modulation | — | Ultra-Narrow-Band (UNB), DBPSK uplink |
| Maximum Payload Size | — | 12 bytes per uplink message |
| Form Factor | — | Surface-mount LGA castellation module |
| RoHS 狀態 | — | Compliant |