RC28F128P33B85B - 128Mbit NOR Flash, 52MHz, 85ns, 64-EasyBGA | Intel/Altera
MPN： RC28F128P33B85B ✗ 停產RC28F128P33B85B 概覽
A NOR Flash memory is a non-volatile storage technology that provides random read access at byte or word granularity, in contrast to NAND Flash which is read in large pages. NOR Flash retains code directly executable in-place (XIP), making it the historical choice for boot ROM, firmware storage, and embedded systems where deterministic read latency matters. Within the memory hierarchy, NOR Flash sits above NAND Flash and below SRAM/DRAM, trading higher density for fast random reads and long-term data retention.
Key features of the RC28F128P33B85B include 128 Mbit (16 Mbyte) density, x16 data bus, Common Flash Interface (CFI) for vendor-independent identification, 33-bit hardware ECC, and a uniform 64-Kbyte symmetric block architecture with configurable read-while-write (RWW) capability. The P33 process technology delivers lower power consumption and faster program/erase times than earlier Numonyx/Intel P30 devices.
This part supports simultaneous read-while-write operations, allowing the host CPU to fetch instructions from one bank while another bank is being programmed or erased. The EasyBGA-64 (8x10 mm) package offers a compact footprint suitable for space-limited embedded designs while exposing the full multiplexed address/data bus needed for legacy parallel interfaces.
Typical applications include embedded boot ROM for networking equipment, industrial control firmware storage, automotive telematics and infotainment code storage, and legacy parallel-interface designs that require deterministic read latency. The 52 MHz synchronous burst-read mode also enables higher-throughput data streaming.
When designing with this device, ensure the host platform supports the legacy CFI query protocol and the 33-bit hardware ECC engine for production-grade reliability. Designers transitioning from older Numonyx/Intel P30 devices must verify pinout compatibility, as the EasyBGA ball map differs from earlier TSOP packaging.
This page synthesizes distributor pricing from LCSC, DigiKey Marketplace and Octopart, drop-in package-compatible alternatives from the same P33 family, and practical design considerations not consolidated in the manufacturer datasheet.
直接替換替代品，適用於 RC28F128P33B85B — 相同封裝，腳位對腳位相容。需重新設計 PCB 的不同封裝零件不列入。
RC28F128P33B85A
✅ 直接替換📋 參考替代品（不在目錄中）
RC28F128P33T85
✅ 直接替換📋 參考替代品（不在目錄中）
PC28F128P33B85
✅ 直接替換📋 參考替代品（不在目錄中）
PC28F128P33B85E
✅ 直接替換📋 參考替代品（不在目錄中）
S29GL128P11TFI020
✅ 直接替換📋 參考替代品（不在目錄中）
W29GL128CL7S
✅ 直接替換📋 參考替代品（不在目錄中）
RC28F128P33B85B 最大額定值與電氣特性
| 記憶體類型 | NOR Flash |
| 記憶體容量 | 128 Mbit (16 Mbyte) |
| Memory Organization | 8M x 16 |
| 介面類型 | Parallel CFI |
| Clock Frequency (Synchronous Read) | 52 MHz |
| Initial Access Time | 85 ns |
| 供應電壓 | 2.5 V / 3.3 V (dual-voltage) |
| Program/Erase Technology | StrataFlash P33 (90 nm) |
| Block Architecture | 64-Kbyte uniform symmetric blocks |
| Read-While-Write | Yes (configurable RWW) |
| Hardware ECC | 33-bit on-die ECC |
| 封裝 | 64-ball EasyBGA (8x10 mm) |
| 安裝類型 | Surface Mount |
| 工作溫度 | -40C to +85C (industrial) |
| RoHS 狀態 | Compliant |
RC28F128P33B85B 腳位配置
| 腳位 A1 | NC — No connect (per datasheet EasyBGA-64 ball map) |
| 腳位 A2 | NC — No connect |
| 腳位 A3 | A15 — Address input A15 |
| 腳位 A4 | A14 — Address input A14 |
| 腳位 A5 | A13 — Address input A13 |
| 腳位 A6 | A12 — Address input A12 |
| 腳位 A7 | A11 — Address input A11 |
| 腳位 A8 | A9 — Address input A9 |
| 腳位 B1 | RY/BY# — Ready/Busy output (open drain) |
| 腳位 B2 | WE# — Write Enable (active low) |
| 腳位 B3 | DQ15/A-1 — Data DQ15 / Address -1 (word mode) |
| 腳位 B4 | DQ7 — Data I/O DQ7 |
| 腳位 B5 | DQ5 — Data I/O DQ5 |
| 腳位 B6 | DQ3 — Data I/O DQ3 |
| 腳位 B7 | DQ1 — Data I/O DQ1 |
| 腳位 B8 | VSS — Ground |
| 腳位 C1 | CE# — Chip Enable (active low) |
| 腳位 C2 | OE# — Output Enable (active low) |
| 腳位 C3 | ADV# — Address Valid (active low) |
| 腳位 C4 | DQ13 — Data I/O DQ13 |
| 腳位 C5 | DQ11 — Data I/O DQ11 |
| 腳位 C6 | DQ9 — Data I/O DQ9 |
| 腳位 C7 | VCCQ — I/O supply voltage (2.5V/3.3V) |
| 腳位 C8 | VCC — Core supply voltage |
| 腳位 D1 | WP# — Write Protect (active low) |
| 腳位 D2 | CLK — Synchronous read clock input |
| 腳位 D3 | DQ14 — Data I/O DQ14 |
| 腳位 D4 | DQ12 — Data I/O DQ12 |
| 腳位 D5 | DQ10 — Data I/O DQ10 |
| 腳位 D6 | DQ8 — Data I/O DQ8 |
| 腳位 D7 | DQ6 — Data I/O DQ6 |
| 腳位 D8 | DQ4 — Data I/O DQ4 |
| 腳位 E1 | A22 — Address input A22 |
| 腳位 E2 | A21 — Address input A21 |
| 腳位 E3 | A20 — Address input A20 |
| 腳位 E4 | A19 — Address input A19 |
| 腳位 E5 | A18 — Address input A18 |
| 腳位 E6 | A17 — Address input A17 |
| 腳位 E7 | A16 — Address input A16 |
| 腳位 E8 | A10 — Address input A10 |
| 腳位 F1 | NC — No connect |
| 腳位 F2 | NC — No connect |
| 腳位 F3 | VSS — Ground |
| 腳位 F4 | VSS — Ground |
| 腳位 F5 | VSS — Ground |
| 腳位 F6 | VCC — Core supply voltage |
| 腳位 F7 | VCC — Core supply voltage |
| 腳位 F8 | DQ2 — Data I/O DQ2 |
| 腳位 G1 | NC — No connect |
| 腳位 G2 | NC — No connect |
| 腳位 G3 | A0 — Address input A0 |
| 腳位 G4 | A1 — Address input A1 |
| 腳位 G5 | A2 — Address input A2 |
| 腳位 G6 | A3 — Address input A3 |
| 腳位 G7 | A4 — Address input A4 |
| 腳位 G8 | A5 — Address input A5 |
| 腳位 H1 | NC — No connect |
| 腳位 H2 | NC — No connect |
| 腳位 H3 | VSS — Ground |
| 腳位 H4 | VSS — Ground |
| 腳位 H5 | VSS — Ground |
| 腳位 H6 | VCC — Core supply voltage |
| 腳位 H7 | VCCQ — I/O supply voltage |
| 腳位 H8 | DQ0 — Data I/O DQ0 |
典型應用
RC28F128P33B85B 適用於 6 應用s: Embedded Boot ROM for Networking Equipment, Industrial Control Firmware Storage, Automotive Infotainment Code Storage, Legacy Parallel-Interface Embedded Designs, Firmware Update Storage with Redundancy, Test and Measurement Equipment Data Logging.
Embedded Boot ROM for Networking Equipment
The RC28F128P33B85B is well suited as the boot ROM in routers, switches and base stations because its 85 ns random access and 52 MHz synchronous burst mode support deterministic execute-in-place (XIP) at typical CPU clock speeds. The 16 Mbyte density stores full bootloaders plus secondary recovery images, and the read-while-write architecture enables firmware updates without taking the system offline. Its 2.5 V/3.3 V supply matches the legacy parallel bus found in many PowerPC and MIPS networking SoCs, eliminating level-translation overhead.
推薦
Industrial Control Firmware Storage
In PLCs, HMIs and motor controllers, the RC28F128P33B85B stores application firmware plus configuration data with industrial -40C to +85C temperature grading. Its 33-bit on-die hardware ECC provides production-grade reliability for long-life industrial equipment, and the EasyBGA-64 (8x10 mm) compact footprint fits within densely populated control boards. Read-while-write allows live firmware patching without halting the control loop, which is critical for continuous-process industries.
推薦
Automotive Infotainment Code Storage
Although the standard RC28F128P33B85B is industrial-grade (-40C to +85C) rather than AEC-Q100 qualified, it has historically been used in non-safety-critical automotive infotainment and telematics applications where its 128 Mbit density stores navigation maps, media assets and application code. Its parallel x16 bus delivers sufficient throughput for streaming audio/video metadata, and the EasyBGA-64 package withstands automotive thermomechanical stress. For safety-critical ADAS systems, an AEC-Q100 qualified alternative is required.
推薦
Legacy Parallel-Interface Embedded Designs
Designers maintaining x86 embedded platforms, legacy PowerPC designs, or older MIPS controllers benefit from the RC28F128P33B85B's standard CFI parallel interface and multiplexed address/data bus. The 85 ns access time accommodates 25-40 MHz host bus frequencies without wait states, and the JEDEC CFI query protocol allows the bootloader to identify the part without proprietary commands. This makes it ideal for long-lifecycle designs in medical, defense and industrial automation where board respins are expensive.
推薦
Firmware Update Storage with Redundancy
The RC28F128P33B85B's read-while-write feature makes it ideal for A/B firmware partition schemes where one bank holds the active image and another receives the update. The 128 Mbit density accommodates two complete 8 Mbyte firmware images plus a non-volatile configuration block. The 33-bit ECC engine corrects bit errors induced by long retention or radiation, which is essential for medical and aerospace systems where data integrity is non-negotiable.
推薦
Test and Measurement Equipment Data Logging
Oscilloscopes, spectrum analyzers and data-acquisition systems leverage the RC28F128P33B85B for non-volatile capture storage where 128 Mbit holds hundreds of waveform records. Its 52 MHz synchronous burst read mode enables fast recall of stored captures to the display processor, and the hardware ECC preserves calibration constants against bit rot over the equipment's multi-decade service life. The industrial temperature rating suits bench and field-deployed instruments.
推薦
推薦產品摘要
工程參考資料，適用於 RC28F128P33B85B — 比較、設計指引及合規資訊。
選型指南
與替代品比較
| 參數 | 本產品 | RC28F128P33B85A | RC28F128P33T85 | PC28F128P33B85 | S29GL128P11TFI020 | W29GL128CL7S |
|---|---|---|---|---|---|---|
| Brand | Intel (Rochester) | Micron Technology | Intel | Intel | Cypress Semiconductor | Winbond |
| Package | 64-EasyBGA (8x10) | 64-EasyBGA (8x10) - same | 64-EasyBGA (8x10) - same | 64-EasyBGA (8x10) - same | 64-EasyBGA (8x10) - same | 64-EasyBGA (8x10) - same |
| Memory Density | 128 Mbit | 128 Mbit | 128 Mbit | 128 Mbit | 128 Mbit | 128 Mbit |
| Initial Access Time | 85 ns | 85 ns | 85 ns | 85 ns | 110 ns | 70 ns |
| Organization | 8M x 16 | 8M x 16 | 8M x 16 | 8M x 16 | 16M x 8 / 8M x 16 | 16M x 8 / 8M x 16 |
| Operating Temperature | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C |
| Supply Voltage | 2.5V / 3.3V | 2.5V / 3.3V | 2.5V / 3.3V | 2.5V / 3.3V | 3.0V | 2.7V to 3.6V |
主要差異化特點
- EasyBGA-64 with 33-bit on-die ECC (對比S29GL128P11TFI020 (Cypress))
- Read-While-Write partition banking (對比W29GL128CL7S (Winbond))
- CFI compliance with Intel legacy command set (對比W29GL128CL7S (Winbond))
設計說明
EasyBGA-64 packages require PCB pad design per JEDEC BGA guidelines - use NSMD (non-solder-mask-defined) pads with 0.5 mm diameter and 1.0 mm pitch. Vias-in-pad with filled and plated-over copper are recommended for the inner balls to improve thermomechanical reliability and signal integrity for the multiplexed address/data bus. Reference the Intel StrataFlash P33 hardware design guide for the recommended 4-layer stackup.
The 52 MHz synchronous read mode requires series damping resistors (22-33 ohm) on DQ[15:0] near the flash to suppress reflections from the host memory controller. Trace length matching within 100 mils across the byte lane is essential. Place 0.1 uF X7R decoupling capacitors adjacent to every VCC and VCCQ ball, with bulk 4.7 uF tantalum or ceramic on each supply rail.
Do not assume RC28F128P33B85B software commands are pin-compatible with older P30 or Numonyx M28W parts - the command set, status register layout and CFI query structure changed in the P33 generation. Reprogram your flash translation layer (FTL) or device driver using the latest Intel specification upgrade command set. Failure to do so can corrupt blocks or yield unreliable ECC reports.
During program and erase operations, VCC current can spike to 50 mA per bank. Decoupling must hold VCC within 5% during these transients. Add a 10 uF bulk capacitor per EasyBGA device plus 0.1 uF bypass on every supply pin. Read-while-write operations require both banks to have independent decoupling; do not share bulk capacitors between parallel-mounted flashes.
合規資訊
RoHS compliant per LCSC and Lisleapex listings. Industrial temperature grade (-40C to +85C) is not AEC-Q100 qualified; select AEC-Q100 variant for safety-critical automotive.
