RC28F128P33B85B - 128Mbit NOR Flash, 52MHz, 85ns, 64-EasyBGA | Intel/Altera
料号： RC28F128P33B85B ✗ 停产| 数量 | 单价 | 小计 |
|---|---|---|
| 1 | $1.45 | $1.45 |
| 10 | $1.38 | $13.80 |
| 100 | $1.27 | $127.00 |
| 500 | $1.18 | $590.00 |
| 1,000 | $1.1 | $1,100.00 |
RC28F128P33B85B 概述
A NOR Flash memory is a non-volatile storage technology that provides random read access at byte or word granularity, in contrast to NAND Flash which is read in large pages. NOR Flash retains code directly executable in-place (XIP), making it the historical choice for boot ROM, firmware storage, and embedded systems where deterministic read latency matters. Within the memory hierarchy, NOR Flash sits above NAND Flash and below SRAM/DRAM, trading higher density for fast random reads and long-term data retention.
Key features of the RC28F128P33B85B include 128 Mbit (16 Mbyte) density, x16 data bus, Common Flash Interface (CFI) for vendor-independent identification, 33-bit hardware ECC, and a uniform 64-Kbyte symmetric block architecture with configurable read-while-write (RWW) capability. The P33 process technology delivers lower power consumption and faster program/erase times than earlier Numonyx/Intel P30 devices.
This part supports simultaneous read-while-write operations, allowing the host CPU to fetch instructions from one bank while another bank is being programmed or erased. The EasyBGA-64 (8x10 mm) package offers a compact footprint suitable for space-limited embedded designs while exposing the full multiplexed address/data bus needed for legacy parallel interfaces.
Typical applications include embedded boot ROM for networking equipment, industrial control firmware storage, automotive telematics and infotainment code storage, and legacy parallel-interface designs that require deterministic read latency. The 52 MHz synchronous burst-read mode also enables higher-throughput data streaming.
When designing with this device, ensure the host platform supports the legacy CFI query protocol and the 33-bit hardware ECC engine for production-grade reliability. Designers transitioning from older Numonyx/Intel P30 devices must verify pinout compatibility, as the EasyBGA ball map differs from earlier TSOP packaging.
This page synthesizes distributor pricing from LCSC, DigiKey Marketplace and Octopart, drop-in package-compatible alternatives from the same P33 family, and practical design considerations not consolidated in the manufacturer datasheet.
直接替换替代料： RC28F128P33B85B ——相同封装，引脚兼容。需要 PCB 改动的不同封装料号已排除。
快速对比工具——选择替代料号进行并排对比：
RC28F128P33B85A
✅ 直接替换📋 参考替代料（不在目录中）
RC28F128P33T85
✅ 直接替换📋 参考替代料（不在目录中）
PC28F128P33B85
✅ 直接替换📋 参考替代料（不在目录中）
PC28F128P33B85E
✅ 直接替换📋 参考替代料（不在目录中）
S29GL128P11TFI020
✅ 直接替换📋 参考替代料（不在目录中）
W29GL128CL7S
✅ 直接替换📋 参考替代料（不在目录中）
RC28F128P33B85B 最大额定值与电气特性
| 存储器类型 | NOR Flash |
| 存储容量 | 128 Mbit (16 Mbyte) |
| Memory Organization | 8M x 16 |
| 接口类型 | Parallel CFI |
| Clock Frequency (Synchronous Read) | 52 MHz |
| Initial Access Time | 85 ns |
| 电源电压 | 2.5 V / 3.3 V (dual-voltage) |
| Program/Erase Technology | StrataFlash P33 (90 nm) |
| Block Architecture | 64-Kbyte uniform symmetric blocks |
| Read-While-Write | Yes (configurable RWW) |
| Hardware ECC | 33-bit on-die ECC |
| 封装 | 64-ball EasyBGA (8x10 mm) |
| 安装类型 | Surface Mount |
| 工作温度 | -40C to +85C (industrial) |
| RoHS 状态 | Compliant |
RC28F128P33B85B 引脚配置
| 引脚 A1 | NC — No connect (per datasheet EasyBGA-64 ball map) |
| 引脚 A2 | NC — No connect |
| 引脚 A3 | A15 — Address input A15 |
| 引脚 A4 | A14 — Address input A14 |
| 引脚 A5 | A13 — Address input A13 |
| 引脚 A6 | A12 — Address input A12 |
| 引脚 A7 | A11 — Address input A11 |
| 引脚 A8 | A9 — Address input A9 |
| 引脚 B1 | RY/BY# — Ready/Busy output (open drain) |
| 引脚 B2 | WE# — Write Enable (active low) |
| 引脚 B3 | DQ15/A-1 — Data DQ15 / Address -1 (word mode) |
| 引脚 B4 | DQ7 — Data I/O DQ7 |
| 引脚 B5 | DQ5 — Data I/O DQ5 |
| 引脚 B6 | DQ3 — Data I/O DQ3 |
| 引脚 B7 | DQ1 — Data I/O DQ1 |
| 引脚 B8 | VSS — Ground |
| 引脚 C1 | CE# — Chip Enable (active low) |
| 引脚 C2 | OE# — Output Enable (active low) |
| 引脚 C3 | ADV# — Address Valid (active low) |
| 引脚 C4 | DQ13 — Data I/O DQ13 |
| 引脚 C5 | DQ11 — Data I/O DQ11 |
| 引脚 C6 | DQ9 — Data I/O DQ9 |
| 引脚 C7 | VCCQ — I/O supply voltage (2.5V/3.3V) |
| 引脚 C8 | VCC — Core supply voltage |
| 引脚 D1 | WP# — Write Protect (active low) |
| 引脚 D2 | CLK — Synchronous read clock input |
| 引脚 D3 | DQ14 — Data I/O DQ14 |
| 引脚 D4 | DQ12 — Data I/O DQ12 |
| 引脚 D5 | DQ10 — Data I/O DQ10 |
| 引脚 D6 | DQ8 — Data I/O DQ8 |
| 引脚 D7 | DQ6 — Data I/O DQ6 |
| 引脚 D8 | DQ4 — Data I/O DQ4 |
| 引脚 E1 | A22 — Address input A22 |
| 引脚 E2 | A21 — Address input A21 |
| 引脚 E3 | A20 — Address input A20 |
| 引脚 E4 | A19 — Address input A19 |
| 引脚 E5 | A18 — Address input A18 |
| 引脚 E6 | A17 — Address input A17 |
| 引脚 E7 | A16 — Address input A16 |
| 引脚 E8 | A10 — Address input A10 |
| 引脚 F1 | NC — No connect |
| 引脚 F2 | NC — No connect |
| 引脚 F3 | VSS — Ground |
| 引脚 F4 | VSS — Ground |
| 引脚 F5 | VSS — Ground |
| 引脚 F6 | VCC — Core supply voltage |
| 引脚 F7 | VCC — Core supply voltage |
| 引脚 F8 | DQ2 — Data I/O DQ2 |
| 引脚 G1 | NC — No connect |
| 引脚 G2 | NC — No connect |
| 引脚 G3 | A0 — Address input A0 |
| 引脚 G4 | A1 — Address input A1 |
| 引脚 G5 | A2 — Address input A2 |
| 引脚 G6 | A3 — Address input A3 |
| 引脚 G7 | A4 — Address input A4 |
| 引脚 G8 | A5 — Address input A5 |
| 引脚 H1 | NC — No connect |
| 引脚 H2 | NC — No connect |
| 引脚 H3 | VSS — Ground |
| 引脚 H4 | VSS — Ground |
| 引脚 H5 | VSS — Ground |
| 引脚 H6 | VCC — Core supply voltage |
| 引脚 H7 | VCCQ — I/O supply voltage |
| 引脚 H8 | DQ0 — Data I/O DQ0 |
典型应用
RC28F128P33B85B 适用于 6 应用s: Embedded Boot ROM for Networking Equipment, Industrial Control Firmware Storage, Automotive Infotainment Code Storage, Legacy Parallel-Interface Embedded Designs, Firmware Update Storage with Redundancy, Test and Measurement Equipment Data Logging.
Embedded Boot ROM for Networking Equipment
The RC28F128P33B85B is well suited as the boot ROM in routers, switches and base stations because its 85 ns random access and 52 MHz synchronous burst mode support deterministic execute-in-place (XIP) at typical CPU clock speeds. The 16 Mbyte density stores full bootloaders plus secondary recovery images, and the read-while-write architecture enables firmware updates without taking the system offline. Its 2.5 V/3.3 V supply matches the legacy parallel bus found in many PowerPC and MIPS networking SoCs, eliminating level-translation overhead.
推荐
Industrial Control Firmware Storage
In PLCs, HMIs and motor controllers, the RC28F128P33B85B stores application firmware plus configuration data with industrial -40C to +85C temperature grading. Its 33-bit on-die hardware ECC provides production-grade reliability for long-life industrial equipment, and the EasyBGA-64 (8x10 mm) compact footprint fits within densely populated control boards. Read-while-write allows live firmware patching without halting the control loop, which is critical for continuous-process industries.
推荐
Automotive Infotainment Code Storage
Although the standard RC28F128P33B85B is industrial-grade (-40C to +85C) rather than AEC-Q100 qualified, it has historically been used in non-safety-critical automotive infotainment and telematics applications where its 128 Mbit density stores navigation maps, media assets and application code. Its parallel x16 bus delivers sufficient throughput for streaming audio/video metadata, and the EasyBGA-64 package withstands automotive thermomechanical stress. For safety-critical ADAS systems, an AEC-Q100 qualified alternative is required.
推荐
Legacy Parallel-Interface Embedded Designs
Designers maintaining x86 embedded platforms, legacy PowerPC designs, or older MIPS controllers benefit from the RC28F128P33B85B's standard CFI parallel interface and multiplexed address/data bus. The 85 ns access time accommodates 25-40 MHz host bus frequencies without wait states, and the JEDEC CFI query protocol allows the bootloader to identify the part without proprietary commands. This makes it ideal for long-lifecycle designs in medical, defense and industrial automation where board respins are expensive.
推荐
Firmware Update Storage with Redundancy
The RC28F128P33B85B's read-while-write feature makes it ideal for A/B firmware partition schemes where one bank holds the active image and another receives the update. The 128 Mbit density accommodates two complete 8 Mbyte firmware images plus a non-volatile configuration block. The 33-bit ECC engine corrects bit errors induced by long retention or radiation, which is essential for medical and aerospace systems where data integrity is non-negotiable.
推荐
Test and Measurement Equipment Data Logging
Oscilloscopes, spectrum analyzers and data-acquisition systems leverage the RC28F128P33B85B for non-volatile capture storage where 128 Mbit holds hundreds of waveform records. Its 52 MHz synchronous burst read mode enables fast recall of stored captures to the display processor, and the hardware ECC preserves calibration constants against bit rot over the equipment's multi-decade service life. The industrial temperature rating suits bench and field-deployed instruments.
推荐
推荐产品汇总
工程参考数据： RC28F128P33B85B ——对比、设计指导和合规信息。
选型指南
与替代料对比
| 参数 | 本产品 | RC28F128P33B85A | RC28F128P33T85 | PC28F128P33B85 | S29GL128P11TFI020 | W29GL128CL7S |
|---|---|---|---|---|---|---|
| Brand | Intel (Rochester) | Micron Technology | Intel | Intel | Cypress Semiconductor | Winbond |
| Package | 64-EasyBGA (8x10) | 64-EasyBGA (8x10) - same | 64-EasyBGA (8x10) - same | 64-EasyBGA (8x10) - same | 64-EasyBGA (8x10) - same | 64-EasyBGA (8x10) - same |
| Memory Density | 128 Mbit | 128 Mbit | 128 Mbit | 128 Mbit | 128 Mbit | 128 Mbit |
| Initial Access Time | 85 ns | 85 ns | 85 ns | 85 ns | 110 ns | 70 ns |
| Organization | 8M x 16 | 8M x 16 | 8M x 16 | 8M x 16 | 16M x 8 / 8M x 16 | 16M x 8 / 8M x 16 |
| Operating Temperature | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C |
| Supply Voltage | 2.5V / 3.3V | 2.5V / 3.3V | 2.5V / 3.3V | 2.5V / 3.3V | 3.0V | 2.7V to 3.6V |
关键差异点
- EasyBGA-64 with 33-bit on-die ECC （对比 S29GL128P11TFI020 (Cypress))
- Read-While-Write partition banking （对比 W29GL128CL7S (Winbond))
- CFI compliance with Intel legacy command set （对比 W29GL128CL7S (Winbond))
设计说明
EasyBGA-64 packages require PCB pad design per JEDEC BGA guidelines - use NSMD (non-solder-mask-defined) pads with 0.5 mm diameter and 1.0 mm pitch. Vias-in-pad with filled and plated-over copper are recommended for the inner balls to improve thermomechanical reliability and signal integrity for the multiplexed address/data bus. Reference the Intel StrataFlash P33 hardware design guide for the recommended 4-layer stackup.
The 52 MHz synchronous read mode requires series damping resistors (22-33 ohm) on DQ[15:0] near the flash to suppress reflections from the host memory controller. Trace length matching within 100 mils across the byte lane is essential. Place 0.1 uF X7R decoupling capacitors adjacent to every VCC and VCCQ ball, with bulk 4.7 uF tantalum or ceramic on each supply rail.
Do not assume RC28F128P33B85B software commands are pin-compatible with older P30 or Numonyx M28W parts - the command set, status register layout and CFI query structure changed in the P33 generation. Reprogram your flash translation layer (FTL) or device driver using the latest Intel specification upgrade command set. Failure to do so can corrupt blocks or yield unreliable ECC reports.
During program and erase operations, VCC current can spike to 50 mA per bank. Decoupling must hold VCC within 5% during these transients. Add a 10 uF bulk capacitor per EasyBGA device plus 0.1 uF bypass on every supply pin. Read-while-write operations require both banks to have independent decoupling; do not share bulk capacitors between parallel-mounted flashes.
合规信息
RoHS compliant per LCSC and Lisleapex listings. Industrial temperature grade (-40C to +85C) is not AEC-Q100 qualified; select AEC-Q100 variant for safety-critical automotive.
