Reported by TechPowerUp on 2026-10-16. Summarized and analyzed by XAIPART Editorial.
What happened
Bare-die photographs of Intel's upcoming mobile "Nova Lake" processors have been published by the Moore's Law Is Dead YouTube channel, showing the package layout of both the "Nova Lake-HX" and "Nova Lake-H" variants.S1
The top "Nova Lake-HX" part uses an 8 P-Core plus 16 E-Core plus 4 LPE-Core configuration and ships in a 12x30 mm package totaling 360 mm² across six tiles.S1
Its compute tile holds the 8P+16E cores on the TSMC N2P node at 104 mm², the largest single die in the package.S1
The graphics tile embeds 4 Xe GPU cores on Intel 3-E at roughly 26 mm²; a central hub die on Intel 18A-P hosts the 4 LPE-Cores at 72 mm²; a peripheral control die sits beside it at 58 mm² on the same 18A-P node; a 21 mm² dummy die is used for structural integrity; and a separate 85 mm² passive die is placed beside the compute tile for structural and operational support.S1
The lower-tier "Nova Lake-H" uses a 4P+8E+4LPE setup in a smaller 12x23 mm package, 276 mm² total. The compute tile carries 4P+8E on TSMC N2P and shrinks to 55 mm², with an adjacent 45 mm² passive die. The peripheral, central hub, and graphics tiles retain the same sizes and Intel nodes as in the HX part.S1
| Metric | Reported |
|---|---|
| Nova Lake-HX core config | 8P + 16E + 4 LPE |
| Nova Lake-HX package size / area | 12 x 30 mm / 360 mm² |
| Nova Lake-HX compute tile (TSMC N2P) | 104 mm² |
| Nova Lake-HX graphics tile (Intel 3-E) | ~26 mm², 4 Xe cores |
| Nova Lake-HX hub die / peripheral die (Intel 18A-P) | 72 mm² / 58 mm² |
| Nova Lake-HX passive die / dummy die | 85 mm² / 21 mm² |
| Nova Lake-H core config | 4P + 8E + 4 LPE |
| Nova Lake-H package size / area | 12 x 23 mm / 276 mm² |
| Nova Lake-H compute tile (TSMC N2P) | 55 mm² |
| Nova Lake-H passive die | 45 mm² |
| HX power, clocks, launch date, pricing | Not disclosed |
| H power, clocks, launch date, pricing | Not disclosed |
Background timeline
- No prior milestones disclosed by the source.
XAIPART take
Technical impact
The package map codifies a chiplet approach in which Intel keeps the iGPU, hub, and I/O control tiles on internal 18A-P and Intel 3-E processes, while outsourcing the heavy compute tile to TSMC N2P. XAIPART analysis: in plain procurement terms, this means at least two separate foundry supply lines feed every Nova Lake mobile SKU, with the compute tile carrying the bulk of the die area and therefore the largest share of wafer consumption.
Market impact
Because the part reuses identical hub, peripheral, and graphics tiles across both SKUs, Intel can bin and yield these dies once and pair them with two compute-tile sizes (104 mm² vs 55 mm²). XAIPART analysis: that shared-tile strategy should help stabilize mobile-platform allocations relative to a monolithic die, although buyers should still plan for TSMC N2P-driven timing risk on the compute tile.
Action
Design teams evaluating Nova Lake-HX or -H should freeze system thermal budgets once Intel publishes TDP figures (not disclosed here) and cross-check that the 12x30 mm / 12x23 mm package footprints fit existing socket or BGA keep-out zones. XAIPART analysis: for now it is wise to lock the hub and iGPU block-diagrams from this shot, then wait for an official Intel block diagram before committing to a final BOM revision.
XAIPART Forecast
If Intel discloses the Nova Lake-HX TDP at or below 55 W, this forecast is confirmed; if it lands above 75 W, the forecast is wrong. XAIPART analysis: XAIPART expects an official block diagram for Nova Lake-HX to appear within 9 months (by Q3 2027), based on the cadence between prior Meteor Lake and Lunar Lake disclosures.
Facts are as reported by the cited source. The design-in, sourcing and forward-looking statements above are XAIPART's analysis, not the source's claims. The die-shot images come from a single YouTube source (Moore's Law Is Dead) and have not yet been confirmed against an official Intel block diagram; TDP, launch date, and pricing are not disclosed.
Corrections: none at publication. This brief will be updated with a timestamp if the source corrects its report.
替代料与生命周期
| 料号 | 关系 | 生命周期 | 依据 |
|---|---|---|---|
| — | 暂无收录替代料 待补充数据 | — | 需 match_type 后才可显示任何前代标签 |
“前代”和“替代”标签仅来自已记录的匹配类型、生命周期状态或来源文本。没有记录匹配时,不显示任何标签。我们自己的商品列表不构成市场参考。
关注要点
| 论断 | 阈值 | 发布方 | 状态 |
|---|---|---|---|
| If Intel discloses the Nova Lake-HX TDP at or below 55 W, this forecast is confirmed | it lands above 75 W | Q3 2027 | Pending |
被证明错误的预测仍保留可见并加以标注。我们不会删除它们。
竞争格局
- 23331 个在售商品(XAIPART 此分类)
- 107 收录制造商
- 68 家制造商(过去 30 天内出现在我们的新闻存档中)
统计数据仅反映 XAIPART 目录,不代表市场份额。
受影响的料号
目录中无匹配。 此事件未映射到 XAIPART 当前上架的任何料号。我们不推断匹配,也不显示占位列表。
此事在事件脉络中的位置
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- inno3d-ags-6220v2-packs-eight-rtx-pro-6000-blackwell-server-gpus-in-6u-what-it-means-for-ai-rack-buyers
- intel-nova-lake-hx-and-h-die-shots-surface-six-tile-mobile-package-mapped
- intel-razor-lake-ax-targets-700-tops-what-3-88x-panther-lake-means-for-mobile-ai-boms
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- Nova Lake-HX 和 -H 的裸片照片展示了采用 TSMC N2P、Intel 3-E 和 Intel 18A-P 节点的六芯片移动封装,以及新的核心数量和封装尺寸。 trade
- Intel 表示 Razor Lake-AX 将在 INT8/FP8 下提供 700 TOPS,是 Panther Lake 180 TOPS 的 3.88 倍,采用最高 32 核的 Xe3 iGPU,并重新引入封装内 LPDDR5X/LPDDR6 内存。 trade
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因果链仅由已发布的简报构建——没有简报的节点不会绘制。
各维度成本压力
| Dimension | FRED series ID | Unit | Lag | As of |
|---|---|---|---|---|
| 投入成本 | PCOPPUSDM, PALUMUSDM, PNICKUSDM | USD/mt | 52 d | |
| 供需 | PCU334413334413, IPG3344S | index(1982=100) / index(2017=100) | 46 d | |
| 汇率与能源 | DEXCHUS, DCOILBRENTEU, DHHNGSP | rate / USD/bbl / USD/MMBtu | 5 d |
No free authoritative interface for: gold · silver · rare earth · polysilicon · lithium carbonate · market share — listed rather than approximated.
本文如何生成
过程证据——抓取、来源可靠性检查、模型与校验
| Source fetched | TechPowerUp · www.techpowerup.com · 2,322 chars · fetch status success |
|---|---|
| Source sanity (S1) | ok — passed before any model call (no s1_ block recorded) |
| Model / prompt | MiniMax-M3 · prompt Blog Agent - News Summary (v2.8-final) · 6,667 tokens · 26.7s · run completed |
| Gate | verdict pass · 6/6 applicable checks passed · spec v2.9 · C10 ratio 0.023138 · C10 rounds 0 |
上述每一行均由流水线生成,而非人工撰写。
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