Reported by TechPowerUp on 2026-10-16. Summarized and analyzed by XAIPART Editorial.
What happened
Bare-die photographs of Intel's upcoming mobile "Nova Lake" processors have been published by the Moore's Law Is Dead YouTube channel, showing the package layout of both the "Nova Lake-HX" and "Nova Lake-H" variants.S1
The top "Nova Lake-HX" part uses an 8 P-Core plus 16 E-Core plus 4 LPE-Core configuration and ships in a 12x30 mm package totaling 360 mm² across six tiles.S1
Its compute tile holds the 8P+16E cores on the TSMC N2P node at 104 mm², the largest single die in the package.S1
The graphics tile embeds 4 Xe GPU cores on Intel 3-E at roughly 26 mm²; a central hub die on Intel 18A-P hosts the 4 LPE-Cores at 72 mm²; a peripheral control die sits beside it at 58 mm² on the same 18A-P node; a 21 mm² dummy die is used for structural integrity; and a separate 85 mm² passive die is placed beside the compute tile for structural and operational support.S1
The lower-tier "Nova Lake-H" uses a 4P+8E+4LPE setup in a smaller 12x23 mm package, 276 mm² total. The compute tile carries 4P+8E on TSMC N2P and shrinks to 55 mm², with an adjacent 45 mm² passive die. The peripheral, central hub, and graphics tiles retain the same sizes and Intel nodes as in the HX part.S1
| Metric | Reported |
|---|---|
| Nova Lake-HX core config | 8P + 16E + 4 LPE |
| Nova Lake-HX package size / area | 12 x 30 mm / 360 mm² |
| Nova Lake-HX compute tile (TSMC N2P) | 104 mm² |
| Nova Lake-HX graphics tile (Intel 3-E) | ~26 mm², 4 Xe cores |
| Nova Lake-HX hub die / peripheral die (Intel 18A-P) | 72 mm² / 58 mm² |
| Nova Lake-HX passive die / dummy die | 85 mm² / 21 mm² |
| Nova Lake-H core config | 4P + 8E + 4 LPE |
| Nova Lake-H package size / area | 12 x 23 mm / 276 mm² |
| Nova Lake-H compute tile (TSMC N2P) | 55 mm² |
| Nova Lake-H passive die | 45 mm² |
| HX power, clocks, launch date, pricing | Not disclosed |
| H power, clocks, launch date, pricing | Not disclosed |
Background timeline
- No prior milestones disclosed by the source.
XAIPART take
Technical impact
The package map codifies a chiplet approach in which Intel keeps the iGPU, hub, and I/O control tiles on internal 18A-P and Intel 3-E processes, while outsourcing the heavy compute tile to TSMC N2P. XAIPART analysis: in plain procurement terms, this means at least two separate foundry supply lines feed every Nova Lake mobile SKU, with the compute tile carrying the bulk of the die area and therefore the largest share of wafer consumption.
Market impact
Because the part reuses identical hub, peripheral, and graphics tiles across both SKUs, Intel can bin and yield these dies once and pair them with two compute-tile sizes (104 mm² vs 55 mm²). XAIPART analysis: that shared-tile strategy should help stabilize mobile-platform allocations relative to a monolithic die, although buyers should still plan for TSMC N2P-driven timing risk on the compute tile.
Action
Design teams evaluating Nova Lake-HX or -H should freeze system thermal budgets once Intel publishes TDP figures (not disclosed here) and cross-check that the 12x30 mm / 12x23 mm package footprints fit existing socket or BGA keep-out zones. XAIPART analysis: for now it is wise to lock the hub and iGPU block-diagrams from this shot, then wait for an official Intel block diagram before committing to a final BOM revision.
XAIPART Forecast
If Intel discloses the Nova Lake-HX TDP at or below 55 W, this forecast is confirmed; if it lands above 75 W, the forecast is wrong. XAIPART analysis: XAIPART expects an official block diagram for Nova Lake-HX to appear within 9 months (by Q3 2027), based on the cadence between prior Meteor Lake and Lunar Lake disclosures.
Facts are as reported by the cited source. The design-in, sourcing and forward-looking statements above are XAIPART's analysis, not the source's claims. The die-shot images come from a single YouTube source (Moore's Law Is Dead) and have not yet been confirmed against an official Intel block diagram; TDP, launch date, and pricing are not disclosed.
Corrections: none at publication. This brief will be updated with a timestamp if the source corrects its report.
대체품 및 수명 주기
| 부품 | 관계 | 수명 주기 | 근거 |
|---|---|---|---|
| — | 등록된 대체품 없음 데이터 필요 | — | 요구 사항 match_type 어떤 전임자 라벨이 표시되기 전에 |
"전임자" 및 "대체품" 라벨은 기록된 일치 유형, 수명 주기 상태 또는 출처 텍스트에서만 부여됩니다. 일치가 기록되지 않은 경우 라벨이 표시되지 않습니다. 당사 자체 등록 상품은 시장 기준이 아닙니다.
주시할 사항
| 주장 | 임계값 | 작성: | 상태 |
|---|---|---|---|
| If Intel discloses the Nova Lake-HX TDP at or below 55 W, this forecast is confirmed | it lands above 75 W | Q3 2027 | Pending |
잘못된 예측도 계속 표시하고 표시를 남깁니다. 삭제하지 않습니다.
경쟁 구도
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영향받는 부품
카탈로그 일치 없음. 이 보도는 현재 XAIPART에 등록된 어떤 부품과도 매핑되지 않습니다. 일치를 추론하지 않으며 자리 표시자 목록도 표시하지 않습니다.
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차원별 비용 압력
| Dimension | FRED series ID | Unit | Lag | As of |
|---|---|---|---|---|
| Input cost | PCOPPUSDM, PALUMUSDM, PNICKUSDM | USD/mt | 96 d | |
| Supply/demand | PCU334413334413, IPG3344S | index(1982=100) / index(2017=100) | 46 d | |
| FX & energy | DEXCHUS, DCOILBRENTEU, DHHNGSP | rate / USD/bbl / USD/MMBtu | 6 d |
No free authoritative interface for: gold · silver · rare earth · polysilicon · lithium carbonate · market share — listed rather than approximated.
이 콘텐츠의 제작 방식
프로세스 증거 — 수집, 출처 온전성, 모델 및 게이트
| Source fetched | TechPowerUp · www.techpowerup.com · 2,322 chars · fetch status success |
|---|---|
| Source sanity (S1) | ok — passed before any model call (no s1_ block recorded) |
| Model / prompt | MiniMax-M3 · prompt Blog Agent - News Summary (v2.8-final) · 6,667 tokens · 26.7s · run completed |
| Gate | verdict pass · 6/6 applicable checks passed · spec v2.9 · C10 ratio 0.023138 · C10 rounds 0 |
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