EP610JI-30 vs EP610LI-35 对比
详细并排对比 EP610JI-30 出自 Altera 和 EP610LI-35 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EP610JI-30 | EP610LI-35 |
|---|---|---|
| 品牌 | Altera | Altera |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | 不推荐新设计 | Obsolete |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $9.40 | $10.50 |
| Family | Altera Classic EPLD (EP610) | Classic EPLD |
| Device Type | UV Erasable Programmable Logic Device (EPLD) | — |
| Macrocells | 16 | — |
| Propagation Delay (tpd) | 30 ns (max) | — |
| Pipelined Data Rate | Up to 100 MHz | Up to 100 MHz |
| Product Terms | 160 | 160 |
| Dedicated Inputs | 4 | 4 |
| I/O Pins | 16 | — |
| External Clocks | 2 | — |
| 电源电压 | 5 V (single supply) | 5 V |
| Process Technology | CMOS | CMOS |
| 封装 | CQCC28 (windowed ceramic JLCC, J-bend) | 28-pin PLCC (windowed ceramic, 'LI') |
| Package Code | JLCC-28 / CQCC28 | — |
| Erasure Method | Ultraviolet (UV) via top window | — |
| Programming | Altera Logic Programmer compatible | — |
| 工作温度 | -40C to +85C (industrial, per EP610 family suffix convention) | — |
| 安装类型 | Surface Mount (JLCC) | Surface Mount |
| RoHS 状态 | [DATA_NEEDED: RoHS status - vintage ceramic package, likely non-RoHS] | [DATA_NEEDED: RoHS compliance status] |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Series | — | EP610 |
| Number of Macrocells | — | 16 |
| Usable Gates | — | 300 |
| Number of I/O Pins | — | 16 |
| Total Inputs | — | 20 |
| External Clock Inputs | — | 2 |
| Maximum Propagation Delay | — | 35 ns (tpd) |
| Maximum Operating Frequency | — | 28.6 MHz (fmax) |
| Architecture | — | PAL-type (AND-OR array) |
| 工作温度范围 | — | [DATA_NEEDED: military/industrial operating temperature range] |
| Programming Technology | — | UV-erasable (EPROM) |