EPM5032DM vs EPM5032DI-20 对比
详细并排对比 EPM5032DM 出自 Intel 和 EPM5032DI-20 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EPM5032DM | EPM5032DI-20 |
|---|---|---|
| 品牌 | Intel | Intel |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | Obsolete | Obsolete |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $15.90 | $8.75 |
| Device Family | MAX 5000 | — |
| Macrocells | 32 | 32 |
| Propagation Delay (tPD) | 25 ns | — |
| Usable Gates | 600 to 1000 (typical) | — |
| Logic Inputs | 32 | — |
| Process Technology | CMOS EEPROM | — |
| 封装 | CDIP-28 (ceramic windowed DIP, 28-pin) | Ceramic DIP-20 (windowed, UV-erasable) |
| Supply Voltage (VCC) | 5 V (typical) | — |
| Standby Current | [DATA_NEEDED: ICC standby current] | — |
| 工作温度 | -55C to +125C (military/extended, ceramic package) | Industrial (per 'I' suffix) |
| Programming Technology | UV-erasable (windowed) EEPROM | — |
| Logic Function | Combinational and registered (synchronous) | — |
| Output Polarity | Programmable | — |
| Program Retention | Non-volatile (EEPROM) | — |
| 安装类型 | Through-hole (DIP) | — |
| RoHS 状态 | Non-compliant (ceramic DIP with UV window) | [DATA_NEEDED: RoHS compliance status for ceramic DIP variant] |
| Lead-Free | No (ceramic DIP contains lead) | [DATA_NEEDED: lead-free status] |
| Family | — | MAX 5000 (Altera legacy EPLD) |
| Architecture | — | CMOS PAL-type EPLD with PIA |
| Dedicated Inputs | — | 7 |
| Bidirectional I/O Pins | — | 16 |
| Product Terms | — | 320 (maximum) |
| Flip-Flops | — | 16 (one per macrocell) |
| 最大时钟频率 | — | 62.5 MHz |
| Pin-to-Pin Delay | — | 20 ns (speed grade -20) |
| Programming | — | UV-erasable CMOS, JEDEC fuse file |
| Development Tool | — | Altera MAX+PLUS II (legacy) |