EPM5032DM vs EPM5032DI-20 Comparison
Detailed side-by-side comparison of EPM5032DM by Intel and EPM5032DI-20 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM5032DM | EPM5032DI-20 |
|---|---|---|
| Brand | Intel | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $15.90 | $8.75 |
| Device Family | MAX 5000 | β |
| Macrocells | 32 | 32 |
| Propagation Delay (tPD) | 25 ns | β |
| Usable Gates | 600 to 1000 (typical) | β |
| Logic Inputs | 32 | β |
| Process Technology | CMOS EEPROM | β |
| Package | CDIP-28 (ceramic windowed DIP, 28-pin) | Ceramic DIP-20 (windowed, UV-erasable) |
| Supply Voltage (VCC) | 5 V (typical) | β |
| Standby Current | [DATA_NEEDED: ICC standby current] | β |
| Operating Temperature | -55C to +125C (military/extended, ceramic package) | Industrial (per 'I' suffix) |
| Programming Technology | UV-erasable (windowed) EEPROM | β |
| Logic Function | Combinational and registered (synchronous) | β |
| Output Polarity | Programmable | β |
| Program Retention | Non-volatile (EEPROM) | β |
| Mounting Type | Through-hole (DIP) | β |
| RoHS Status | Non-compliant (ceramic DIP with UV window) | [DATA_NEEDED: RoHS compliance status for ceramic DIP variant] |
| Lead-Free | No (ceramic DIP contains lead) | [DATA_NEEDED: lead-free status] |
| Family | β | MAX 5000 (Altera legacy EPLD) |
| Architecture | β | CMOS PAL-type EPLD with PIA |
| Dedicated Inputs | β | 7 |
| Bidirectional I/O Pins | β | 16 |
| Product Terms | β | 320 (maximum) |
| Flip-Flops | β | 16 (one per macrocell) |
| Maximum Clock Frequency | β | 62.5 MHz |
| Pin-to-Pin Delay | β | 20 ns (speed grade -20) |
| Programming | β | UV-erasable CMOS, JEDEC fuse file |
| Development Tool | β | Altera MAX+PLUS II (legacy) |