24AA64T-E/MS - 64Kb I2C Serial EEPROM, 1.7V | Microchip
料号： 24AA64T-E/MS ✓ 量产中| 数量 | 单价 | 小计 |
|---|---|---|
| 1 | $0.62 | $0.62 |
| 10 | $0.55 | $5.50 |
| 100 | $0.48 | $48.00 |
| 500 | $0.42 | $210.00 |
| 1,000 | $0.36 | $360.00 |
| 2,500 | $0.31 | $775.00 |
24AA64T-E/MS 概述
A serial EEPROM is a type of non-volatile memory that retains stored data without power and is accessed through a low-pin-count serial protocol. In the broader memory hierarchy, EEPROMs sit between byte-alterable NV memory and one-time-programmable (OTP) ROM; the I2C subset specifically targets low-power, board-level configuration storage where two wires (SCL/SDA) are preferred over parallel busses. The 24AA64T-E/MS implements the industry-standard I2C protocol with hardware-selectable slave addresses via A0/A1/A2 pins, enabling up to eight devices on a single bus for 512 Kbit of shared storage.
Key features include 1.7V minimum operating voltage for single-cell Li-ion or coin-cell systems, hardware write protection via the WP pin, 1 million erase/write cycle endurance, and >200-year data retention. The device supports both byte write and 32-byte page write operations, with a built-in 5 ms write-cycle timer that eliminates external polling. A separate data sheet documents Schmitt-triggered SCL/SDA inputs for noise-tolerant bus operation.
Internally, the 24AA64T-E/MS uses a thin-oxide CMOS cell array with a charge-pump-driven high-voltage generator for byte-level programming. The I2C engine implements standard-mode (100 kHz) and fast-mode (400 kHz) timing with input filtering on both bus lines, mitigating the effects of ringing on long PCB traces or shared buses.
Typical applications include consumer-electronics configuration storage (TV backlight and audio settings), medical-device parameter retention, industrial sensor calibration tables, and smart-card / RFID parameter storage. Its 1.7V minimum supply makes it ideal for battery-powered designs where EEPROMs historically required 2.5V or higher.
Designers should use external pull-up resistors (typically 4.7 kohm for 400 kHz) on SCL/SDA, observe the 5 ms write-cycle time, and respect page-boundary alignment for multi-byte writes. The WP pin must be tied low or controlled by the host MCU to allow writes; tying it high hard-protects the entire array.
This page synthesizes distributor pricing, drop-in alternatives, application guidance, and design notes that go beyond the manufacturer datasheet alone, giving engineers a one-stop resource for selecting and applying the 24AA64T-E/MS.
直接替换替代料： 24AA64T-E/MS ——相同封装，引脚兼容。需要 PCB 改动的不同封装料号已排除。
本系列中的变体
可与以下型号直接替换的同系列型号： 24AA64T-E/MS （相同外形与封装尺寸） ——差异在于 Endurance, Memory Size, Memory Type, Operating Temperature, Package.
快速对比工具——选择替代料号进行并排对比：
24AA64T-I/MS
✅ 直接替换📋 参考替代料（不在目录中）
24LC64T-E/MS
✅ 直接替换📋 参考替代料（不在目录中）
24FC64T-I/MS
✅ 直接替换 ⚠️ 规格未核验📋 参考替代料（不在目录中）
AT24C64C-MSHM-T
✅ 直接替换 ⚠️ 规格未核验📋 参考替代料（不在目录中）
BR24L64-WMS
✅ 直接替换📋 参考替代料（不在目录中）
M24C64-WMN6TP
✅ 直接替换📋 参考替代料（不在目录中）
24AA64T-E/MS 最大额定值与电气特性
| 存储器类型 | EEPROM |
| 存储容量 | 64 Kbit (8K x 8) |
| 接口 | I2C (2-wire serial) |
| Clock Frequency (max) | 400 kHz |
| Access Time (max) | 900 ns |
| Supply Voltage (min) | 1.7 V |
| Supply Voltage (max) | 5.5 V |
| Standby Current (typ) | 1 uA |
| Active Current (max) | 3 mA |
| Write Cycle Time (max) | 5 ms |
| Page Size | 32 bytes |
| Endurance | 1,000,000 erase/write cycles |
| Data Retention | >200 years |
| 工作温度 | -40C to +125C (E = extended) |
| 封装 | 8-MSOP |
| 安装类型 | Surface Mount |
| MSL 等级 | 1 (unlimited) |
| RoHS 状态 | Compliant |
24AA64T-E/MS 引脚配置
| 引脚 1 | A0 — User-configurable slave address bit 0 (tie to VCC or GND) |
| 引脚 2 | A1 — User-configurable slave address bit 1 (tie to VCC or GND) |
| 引脚 3 | A2 — User-configurable slave address bit 2 (tie to VCC or GND) |
| 引脚 4 | GND — Ground reference |
| 引脚 5 | SDA — I2C serial data (bidirectional, open-drain, requires pull-up) |
| 引脚 6 | SCL — I2C serial clock input |
| 引脚 7 | WP — Write-protect input (active high = array protected) |
| 引脚 8 | VCC — Supply voltage, 1.7V to 5.5V |
典型应用
24AA64T-E/MS 适用于 7 应用s: Consumer Electronics Configuration Storage, Industrial Sensor Calibration Tables, Medical Device Parameter Retention, Automotive Module Configuration Storage, Smart Card / RFID Parameter Storage, IoT Sensor Node Data Logging, Audio Equipment User-Preference Memory.
Consumer Electronics Configuration Storage
The 24AA64T-E/MS stores user-tunable settings in TVs, set-top boxes, and audio receivers where non-volatile retention across power cycles is required. With 8 Kbytes of addressable space it can hold hundreds of channel presets, equalizer profiles, picture-mode parameters, and parental-control flags. The 1.7V minimum VCC lets it sit directly on a 1.8V rail in fanless appliances. Hardware write-protect via the WP pin allows field firmware updates to lock configuration memory against accidental overwrite, and 200-year retention means the settings outlive the chassis itself.
推荐
Industrial Sensor Calibration Tables
Industrial pressure, load-cell, and gas sensors use the 24AA64T-E/MS to store per-unit calibration coefficients, date-code, and serial number. The 1M-cycle endurance covers millions of field reconfigurations as sensor drift compensation is updated. I2C bus sharing allows the EEPROM to coexist with the sensor's ADC and front-end MCU on the same 2-wire bus. The -40C to +125C extended grade handles outdoor enclosures, factory floors, and under-hood automotive-adjacent environments. The 900 ns access time keeps the calibration-read path well below one I2C byte time.
推荐
Medical Device Parameter Retention
The 24AA64T-E/MS retains therapy parameters, patient log indices, and safety limit tables in portable medical devices such as infusion pumps, glucose meters, and TENS units. The 1.7V minimum supply is critical for single-cell Li-ion or coin-cell powered devices that brown-out below 2.5V. The 1 uA standby current is negligible against typical battery self-discharge, and 200-year data retention exceeds the service life of any portable device. Hardware write-protect prevents accidental patient-data overwrite from firmware bugs.
推荐
Automotive Module Configuration Storage
Body-control modules, instrument clusters, and aftermarket telematics use the 24AA64T-E/MS to store VIN, option codes, mileage, and unit-specific calibration. The -40C to +125C extended grade covers under-dash and under-hood-adjacent compartments. Three hardware address pins allow multi-EEPROM addressing for split-data designs (e.g., one chip for security codes, another for user preferences). The 400 kHz I2C speed is compatible with most automotive-body network MCUs. Although not AEC-Q100 qualified itself, it is widely used in non-safety automotive subsystems.
推荐
Smart Card / RFID Parameter Storage
The 24AA64T-E/MS stores cryptographic keys, ISO 14443 protocol parameters, and reader-configuration tables in contactless smart-card readers. The 32-byte page size aligns well with typical key-block writes. 1M-cycle endurance handles millions of contactless transactions in transit, payment, and access-control deployments. The MSOP footprint enables miniaturized handheld readers. Hardware WP pin lets reader firmware lock cryptographic material after provisioning, providing a tamper-resistance layer against bus-level attacks.
推荐
IoT Sensor Node Data Logging
Battery-powered IoT sensor nodes use the 24AA64T-E/MS to buffer telemetry between wireless transmissions, retaining logs through sleep cycles when RAM contents would otherwise be lost. The 1 uA standby current is comparable to the self-discharge of the host coin cell, making it effectively free at the system level. The 1.7V minimum supply supports single-cell LiMnO2 and alkaline chemistries. 8 Kbytes accommodates thousands of sensor samples with timestamp headers, and I2C bus sharing allows it to coexist with environmental sensors on the same 2-wire bus.
推荐
Audio Equipment User-Preference Memory
Hi-fi amplifiers, headphone DSP units, and stage-lighting consoles use the 24AA64T-E/MS to store EQ presets, channel routing tables, and DMX scene memories. The 8 Kbytes holds dozens of named presets with full parameter snapshots. The 5 ms write cycle lets the host commit user changes with no perceptible latency. I2C bus sharing allows the EEPROM to coexist with audio CODECs and DSP chips that use the same 2-wire interface. -40C to +125C rating handles rack-mount installations with poor ventilation.
推荐
推荐产品汇总
工程参考数据： 24AA64T-E/MS ——对比、设计指导和合规信息。
选型指南
与替代料对比
| 参数 | 本产品 | 24AA64T-I/MS | 24LC64T-E/MS | 24FC64T-I/MS | AT24C64C-MSHM-T | BR24L64-WMS | M24C64-WMN6TP |
|---|---|---|---|---|---|---|---|
| Brand | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology | ROHM Semiconductor | STMicroelectronics |
| Package | 8-MSOP | 8-MSOP - same | 8-MSOP - same | 8-MSOP - same | 8-MSOP - same | 8-MSOP - same | 8-MSOP - same |
| Memory Density | 64 Kbit (8K x 8) | 64 Kbit (8K x 8) | 64 Kbit (8K x 8) | 64 Kbit (8K x 8) | 64 Kbit (8K x 8) | 64 Kbit (8K x 8) | 64 Kbit (8K x 8) |
| Supply Voltage Range | 1.7V to 5.5V | 1.7V to 5.5V | 2.5V to 5.5V | 1.7V to 5.5V | 1.7V to 5.5V | 1.7V to 5.5V | 2.5V to 5.5V |
| Max I2C Clock | 400 kHz | 400 kHz | 400 kHz | 1 MHz | 400 kHz | 400 kHz | 400 kHz |
| Standby Current | 1 uA | 1 uA | 1 uA | 1 uA | 1 uA | 2 uA | 2 uA |
| Operating Temperature | -40C to +125C | -40C to +85C | -40C to +125C | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C |
| Write Cycle Time (max) | 5 ms | 5 ms | 5 ms | 5 ms | 5 ms | 5 ms | 5 ms |
| Write-Protect Pin | Yes (WP) | Yes (WP) | Yes (WP) | Yes (WP) | Yes (WP) | Yes (WP) | Yes (WP) |
关键差异点
- Lowest minimum VCC in its density class （对比 24LC64T-E/MS)
- Extended -40C to +125C operating temperature grade （对比 24AA64T-I/MS)
- Higher endurance than most serial EEPROMs （对比 M24C64-WMN6TP)
设计说明
Always observe the 5 ms write-cycle time after each page or byte write. Issuing a new I2C START before the internal write completes will return a NACK and corrupt the in-progress write. For multi-page writes, either poll the ACK state or use a fixed 6 ms firmware delay per page to guarantee completion. The device returns NACK on SDA during the write cycle, which can be used for ACK-polling without timing assumptions.
Both SDA and SCL require external pull-up resistors. At 400 kHz, use 1 kohm to 4.7 kohm depending on bus capacitance; the standard rule is rise time < 300 ns for fast-mode. Place the EEPROM close to the bus master to minimize stub capacitance, especially when sharing the bus with multiple devices. Add a 100 nF decoupling capacitor as close as practical to the VCC pin to suppress supply noise during write cycles.
Tie unused A0/A1/A2 pins to either VCC or GND - never leave them floating, as a floating address pin can cause the EEPROM to respond to multiple slave addresses and produce bus collisions. If WP is not used, tie it to GND to keep the array writable; if hardware write-protect is required, route WP to a host GPIO rather than hard-wiring it high so firmware can temporarily unlock the array for legitimate writes.
Long I2C traces act as transmission lines above ~400 kHz, and ringing can cause double-clocking. Series-terminate SCL and SDA with 22-33 ohm resistors placed near the bus master, not near the EEPROM, to damp reflections. The 24AA64T-E/MS Schmitt-triggered inputs tolerate moderate ringing, but compliance with the I2C fast-mode rise-time budget (20-300 ns) is the first check if bus errors appear.
Page-write operations must not cross 32-byte page boundaries; doing so silently wraps the address pointer to the start of the same page and corrupts the destination data. When writing more than 32 bytes, split the write into multiple I2C transactions, each no longer than 32 bytes, with a 5 ms delay between transactions. The lower 5 bits of the address counter roll over at page boundaries (8K / 32 = 256 pages).
合规信息
RoHS compliant per Microchip product page. Not AEC-Q100 qualified - not recommended for automotive safety-critical applications. Lead-free and halogen-free per Microchip environmental compliance data. For automotive, choose AEC-Q100 qualified SPI/EEPROM alternatives.
