EPM9560RC-10 - MAX 9000 CPLD, 560 Macrocells, 240-pin PGA | Intel
料号： EPM9560RC-10 ✗ 停产| 数量 | 单价 | 小计 |
|---|---|---|
| 1 | $185 | $185.00 |
| 10 | $165 | $1,650.00 |
| 100 | $140 | $14,000.00 |
| 250 | $125 | $31,250.00 |
| 500 | $110 | $55,000.00 |
EPM9560RC-10 概述
A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that combines multiple PAL-like macrocells on a single chip, providing deterministic timing and instant-on behavior. Within the broader programmable logic hierarchy, the MAX 9000 series sits between classic PLDs (PAL/GAL) and FPGAs, offering glue-logic integration, bus decoding, state-machine encoding, and peripheral interface bridging. It is part of the wider semiconductor category of programmable logic ICs, which includes CPLDs, FPGAs, and SPLDs.
Key features of the EPM9560RC-10 include 16 Logic Array Blocks (LABs) interconnected by the third-generation Multiple Array Matrix (MAX) programmable interconnect, 212 user I/O pins, 5.0 V in-system programmability (ISP) via the IEEE Std. 1149.1 JTAG interface, and built-in boundary-scan test support. The architecture supports each macrocell with up to 32 product terms and a programmable register, enabling efficient implementation of wide combinational and registered logic functions.
Typical applications include high-performance bus-interface bridging, processor glue logic, peripheral controllers, and state-machine implementation in telecommunications, industrial automation, and military/aerospace systems. The 240-pin PGA package also makes the EPM9560RC-10 a strong fit for prototyping and through-hole industrial backplane designs where socketed replacement is preferred over surface-mount rework.
When designing with this device, observe the maximum I/O current ratings and provide proper decoupling on every VCCINT and VCCIO pin pair. The device is non-volatile, so configuration is loaded at power-up with zero boot latency, which simplifies board-level power sequencing compared with SRAM-based FPGAs.
直接替换替代料： EPM9560RC-10 ——相同封装，引脚兼容。需要 PCB 改动的不同封装料号已排除。
本系列中的变体
可与以下型号直接替换的同系列型号： EPM9560RC-10 （相同外形与封装尺寸） ——差异在于 Package, Operating Temperature, Mounting Type, In-System Programmability, Configuration Memory.
快速对比工具——选择替代料号进行并排对比：
EPM9560ARC240-10
✅ 直接替换✓ 有现货
$28.8 / 个
查看数据手册 →EPM9560ARC240-10N
✅ 直接替换✓ 有现货
$19.5 / 个
查看数据手册 →EPM9560ARI240-10
✅ 直接替换✓ 有现货
联系询价
查看数据手册 →EPM9560ARI240-10N
✅ 直接替换✓ 有现货
$105 / 个
查看数据手册 →EPM9560RC-10 最大额定值与电气特性
| Family | MAX 9000 |
| Device Type | CPLD (Complex Programmable Logic Device) |
| Macrocells | 560 |
| Usable Gates | 12,000 |
| Logic Array Blocks (LABs) | 16 |
| Maximum User I/O Pins | 212 |
| Pin-to-Pin Delay (tPD) | 10 ns |
| Supply Voltage (VCCINT/VCCIO) | 5.0 V |
| In-System Programmability | IEEE 1149.1 JTAG |
| Process Technology | CMOS EEPROM |
| Architecture | Multiple Array Matrix (MAX) - third generation |
| 工作温度 | 0C to +70C (commercial) |
| 封装 | 240-pin PGA (RC suffix) |
| 安装类型 | Through-Hole / Socketed |
| RoHS 状态 | unknown |
EPM9560RC-10 240-pin pga (rc suffix) 引脚配置指南
EPM9560RC-10（240-pin pga (rc suffix) 封装）的引脚配置。 该数字 IC 包含 GPIO、通信接口（UART、SPI、I2C）和电源引脚。请参阅制造商数据手册以了解复用引脚功能和配置选项。对嵌入式系统设计和 PCB 布局至关重要。
暂无详细引脚数据： EPM9560RC-10.
请参阅 数据手册 以查看完整引脚配置。
典型应用
EPM9560RC-10 适用于 6 应用s: High-Performance Bus Interface Bridging, Processor Glue Logic and Address Decoding, State-Machine and Protocol Controllers, Legacy Telecom Backplane Logic, Industrial Automation Controllers, Aerospace and Defense Prototype Systems.
High-Performance Bus Interface Bridging
The EPM9560RC-10's 560 macrocells and 212 user I/Os make it ideal for bridging between disparate processor buses in legacy industrial and telecom systems. Its 10 ns tPD allows glue-logic interfaces between 32-bit microprocessors, memory controllers, and peripheral buses without adding wait states. The 5.0 V tolerance matches TTL/CMOS logic levels common in older backplane designs, and the non-volatile EEPROM configuration means zero boot latency. Compared to FPGAs, the MAX 9000 architecture provides deterministic timing - critical for bus-arbiter and handshake logic where races would corrupt data. Place the device near the bus connectors and decouple every VCCINT/VCCIO pair with 0.1 uF ceramics.
推荐
Processor Glue Logic and Address Decoding
With 16 LABs and a robust product-term allocator, the EPM9560RC-10 efficiently implements address decoding, chip-select generation, and wait-state insertion for legacy microprocessors such as the 80x86, 68k, and MIPS families. Its 10 ns propagation delay supports zero-wait-state designs up to ~50 MHz, while 212 I/Os accommodate wide address and data buses plus peripheral control signals. The JTAG ISP interface simplifies board bring-up, allowing engineers to iterate on decode logic without removing the device. Place a 10 kohm pull-up on the JTAG TMS line for clean boundary-scan operation.
推荐
State-Machine and Protocol Controllers
Each macrocell in the EPM9560RC-10 supports a programmable D/T/JK flip-flop and 32 product terms, making the device exceptionally well-suited to large synchronous state machines implementing serial protocols (UART, SPI, I2C), custom peripheral controllers, and sequencing engines. The deterministic MAX interconnect ensures that every state transition completes within a known timing window, eliminating the metastability concerns that plague SRAM-based FPGA designs. Designers can partition complex protocols across multiple LABs while preserving 10 ns-class timing margins for 25-50 Mbps serial links.
推荐
Legacy Telecom Backplane Logic
The EPM9560RC-10's 240-pin ceramic PGA package and 5.0 V tolerance make it a natural fit for legacy telecom backplanes that use TTL bus standards and socketed through-hole components for field serviceability. Its 12,000 usable gates and 212 I/Os can replace multiple 22V10/26V12 PALs and discrete MSI logic, simplifying board layout and improving reliability. The ceramic PGA withstands the wider thermal and mechanical environments of central-office equipment. JTAG ISP enables in-field reconfiguration when protocol updates are required.
推荐
Industrial Automation Controllers
In industrial PLC and motor-control subsystems, the EPM9560RC-10 can replace dozens of discrete logic ICs by integrating encoder decoding, PWM generation, fault handling, and safety interlocks into a single non-volatile device. The 10 ns tPD supports real-time control loops, while the 212 I/Os interface directly to 5 V sensors, optocouplers, and H-bridge drivers. Its deterministic timing avoids the variable-latency issues of microcontrollers running RTOS code, making it ideal for hard-real-time sequencing. Designers should observe derating guidelines for I/O current and add external buffers for high-current loads.
推荐
Aerospace and Defense Prototype Systems
The ceramic PGA package of the EPM9560RC-10 provides the mechanical robustness and thermal performance required for aerospace and defense prototype systems, where socketed CPLDs simplify iterative design and qualification testing. Its 12,000-gate density and 10 ns speed are sufficient for flight-control signal conditioning, sensor-fusion glue logic, and MIL-STD-1553 interface bridging. The non-volatile EEPROM configuration eliminates the need for separate boot PROMs, reducing BOM and improving reliability. Designers should verify radiation-hardness and trace documentation before flight deployment.
推荐
推荐产品汇总
工程参考数据： EPM9560RC-10 ——对比、设计指导和合规信息。
选型指南
与替代料对比
| 参数 | 本产品 | EPM9560ARC240-10 | EPM9560ARC240-10N | EPM9560ARI240-10 | EPM9560ARI240-10N |
|---|---|---|---|---|---|
| Package | 240-pin Ceramic PGA | 240-pin Plastic PGA - same footprint | 240-pin Plastic PGA - same footprint | 240-pin Plastic PGA - same footprint | 240-pin Plastic PGA - same footprint |
| Brand | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) |
| Macrocells | 560 | 560 | 560 | 560 | 560 |
| Speed Grade (tPD) | 10 ns | 10 ns | 10 ns | 10 ns | 10 ns |
| Temperature Grade | Commercial (0C to +70C) | Commercial (0C to +70C) | Commercial (0C to +70C), lead-free | Industrial (-40C to +85C) | Industrial (-40C to +85C), lead-free |
| Package Material | Ceramic | Plastic | Plastic | Plastic | Plastic |
| Lead-Free (N suffix) | Unknown | No | Yes | No | Yes |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
关键差异点
- Ceramic PGA package for high-reliability and socketed serviceability （对比 EPM9560ABC356-10)
- Highest macrocell density in the MAX 9000 family at 560 macrocells （对比 EPM9480RC240-20)
- Commercial temperature grade for cost-sensitive applications （对比 EPM9560ARI240-10)
设计说明
The EPM9560RC-10 requires 5.0 V on both VCCINT (core) and VCCIO (I/O) supply pins. Decouple every VCC/VSS pair with a 0.1 uF X7R ceramic capacitor placed within 5 mm of the pin, and add a bulk 10-47 uF tantalum or aluminum polymer capacitor near the device. The MAX 9000 datasheet recommends one decoupling capacitor per power pin pair to suppress switching noise during simultaneous I/O toggling. The device draws approximately 200-400 mA quiescent current depending on logic utilization and toggle rate; size the regulator accordingly.
The 240-pin ceramic PGA package requires a PGA socket (e.g., a machine-pin socket) for through-hole PCB mounting. Ensure the socket footprint on the PCB matches the standard 240-pin PGA land pattern (24x24 grid with 2.54 mm pitch) and that adequate clearance exists around the socket for the device's ceramic body and heatsink attachment if needed. The ceramic package provides good thermal conductivity (~15 C/W theta_JC), but thermal performance still benefits from a copper heatsink or airflow above 50% macrocell utilization.
Do not assume that any MAX 9000 device with the same speed grade is a drop-in replacement for the EPM9560RC-10 - the package suffix matters. The 'RC' suffix denotes the 240-pin ceramic PGA, while 'ARI240' denotes a 240-pin plastic PGA industrial variant, and 'ABC356' denotes a 356-ball BGA. PCB redesign is required to switch between these packages. Also, note that the -10 speed grade (10 ns tPD) differs from -15 and -20 grades; substituting a slower grade will violate timing budgets. Always check the full MPN including package and speed suffixes.
合规信息
RoHS and lead-free status not explicitly stated in the verified web data. The 'N' suffix in related part numbers (e.g., EPM9560ARC240-10N) indicates a lead-free variant; the EPM9560RC-10 base part number does not carry the N suffix, suggesting it may use SnPb finish consistent with ceramic PGA packaging of that era. Buyers should request a Certificate of Compliance from the distributor for production orders.
