THS1230CDWRG4 - 12-Bit 30 MSPS Low-Power ADC | Texas Instruments
料号： THS1230CDWRG4 ✓ 量产中| 数量 | 单价 | 小计 |
|---|---|---|
| 1 | $9.45 | $9.45 |
| 10 | $8.62 | $86.20 |
| 100 | $7.48 | $748.00 |
| 500 | $6.55 | $3,275.00 |
| 1,000 | $5.92 | $5,920.00 |
THS1230CDWRG4 概述
An analog-to-digital converter (ADC) is a mixed-signal integrated circuit that samples continuous analog voltage signals and converts each sample into a discrete digital code. Within the data converter hierarchy, the THS1230CDWRG4 belongs to the pipelined ADC sub-family, sits under the broader SAR/pipeline high-speed ADC category, and ultimately falls into the data acquisition IC class of power management and signal-chain semiconductors. Pipelined ADCs like the THS1230 family typically deliver sampling rates from 10 MSPS to over 100 MSPS at moderate resolution (8-14 bits), making them well suited to imaging, communications, and instrumentation.
Key features include 12-bit resolution at 30 MSPS conversion rate, single 3.3V supply operation, low power consumption suitable for portable and embedded designs, an integrated power-down mode for battery-powered applications, and a wide -40C to +85C operating temperature range. The configurable analog input structure allows the same device to interface with single-supply sensors, bipolar signals, or differential driver outputs without external translation amplifiers.
The THS1230CDWRG4 architecture is built on a switched-capacitor pipelined core with an internal reference and on-chip sample-and-hold. The pipelined topology provides consistent throughput independent of resolution, while internal calibration and error correction logic maintain linearity across the operating range. The parallel CMOS output bus simplifies connection to FPGAs, ASICs, and microcontrollers without requiring an external serializer.
Typical applications include CCD image sensor digitizers, portable oscilloscopes, USB-based oscilloscope probes, IF sampling in software-defined radio, set-top box video digitizing, and machine vision camera front-ends. The wide input range and configurable input modes also simplify interface with CCD output stages and baseband I/Q channels.
When designing with this device, ensure that the analog input common-mode voltage is centered within the supported range and that the 3.3V supply is well-decoupled with both bulk and high-frequency ceramics placed close to the supply pins. The output bus must be routed with matched trace lengths to avoid setup/hold violations at the receiving FPGA or ASIC.
This page synthesizes distributor pricing, parametric drop-in alternatives, and practical design notes beyond what is contained in the manufacturer datasheet. Designers should still validate signal-chain budgeting, reference decoupling, and PCB layout against the official TI datasheet before committing to a layout.
直接替换替代料： THS1230CDWRG4 ——相同封装，引脚兼容。需要 PCB 改动的不同封装料号已排除。
本系列中的变体
可与以下型号直接替换的同系列型号： THS1230CDWRG4 （相同外形与封装尺寸） ——差异在于 Architecture, Operating Temperature, Package, Power-Down Mode.
快速对比工具——选择替代料号进行并排对比：
THS1230CDW
✅ 直接替换📋 参考替代料（不在目录中）
THS1230CDWR
✅ 直接替换✓ 有现货
$5.2 / 个
查看数据手册 →THS1230IDW
✅ 直接替换📋 参考替代料（不在目录中）
THS1230CDWRG4 最大额定值与电气特性
| 分辨率 | 12 bits |
| Sample Rate | 30 MSPS |
| Number of Inputs | 1 (single channel, configurable) |
| Input Configuration | Single-ended, single-ended w/ offset, differential |
| Analog Input Range | -2 V to +2 V |
| 电源电压 | 3.3 V (single supply) |
| Power-Down Mode | Yes |
| Output Interface | Parallel CMOS |
| ADC Architecture | Pipelined |
| 工作温度 | -40 C to +85 C |
| 封装 | 28-SOIC (DW), 0.295 inch (7.50 mm) width |
| 安装类型 | Surface Mount |
| RoHS 状态 | Compliant |
THS1230CDWRG4 引脚配置
| 引脚 1 | AVDD — Analog supply (3.3 V) |
| 引脚 2 | AINP — Analog input positive (single-ended/differential+) |
| 引脚 3 | AINN — Analog input negative (single-ended/differential-) |
| 引脚 4 | REFP — Reference voltage positive (decoupling) |
| 引脚 5 | REFN — Reference voltage negative (decoupling) |
| 引脚 6 | REFT — Reference top (decoupling) |
| 引脚 7 | REFB — Reference bottom (decoupling) |
| 引脚 8 | AGND — Analog ground |
| 引脚 9 | PD — Power-down input (active high) |
| 引脚 10 | OE — Output enable (active high) |
| 引脚 11 | CLK — Clock input |
| 引脚 12 | DGND — Digital ground |
| 引脚 13 | DVDD — Digital supply (3.3 V) |
| 引脚 14 | D11 — Data output bit 11 (MSB) |
| 引脚 15 | D10 — Data output bit 10 |
| 引脚 16 | D9 — Data output bit 9 |
| 引脚 17 | D8 — Data output bit 8 |
| 引脚 18 | D7 — Data output bit 7 |
| 引脚 19 | D6 — Data output bit 6 |
| 引脚 20 | D5 — Data output bit 5 |
| 引脚 21 | D4 — Data output bit 4 |
| 引脚 22 | D3 — Data output bit 3 |
| 引脚 23 | D2 — Data output bit 2 |
| 引脚 24 | D1 — Data output bit 1 |
| 引脚 25 | D0 — Data output bit 0 (LSB) |
| 引脚 26 | NC — Not connected (per datasheet) |
| 引脚 27 | NC — Not connected (per datasheet) |
| 引脚 28 | NC — Not connected (per datasheet) |
典型应用
THS1230CDWRG4 适用于 7 应用s: CCD Image Sensor Digitizer, Portable Digital Oscilloscope Front-End, Software Defined Radio IF Sampling, Industrial Machine Vision Camera, Set-Top Box Video Digitizer, USB-Based Data Acquisition Module, Ultrasound Beamforming Front-End.
CCD Image Sensor Digitizer
The THS1230CDWRG4 is well matched to CCD image-sensor digitizer front-ends where 12-bit pixel resolution at video-rate clocking is sufficient. Its configurable single-ended with offset input mode lets the on-chip PGA-shaped range accept the typical CCD output swing directly, avoiding an external analog front-end. Designers will typically clock the ADC at 20-30 MSPS to digitize VGA-resolution video streams in real time. The parallel CMOS output bus streams pixel data straight into an FPGA or ASIC image processor without serialization overhead. Compared to a SAR ADC, the pipelined core maintains constant throughput regardless of pixel resolution, simplifying downstream timing closure.
推荐
Portable Digital Oscilloscope Front-End
In portable USB oscilloscopes and bench-top DSOs, the THS1230CDWRG4 provides the 30 MSPS sample rate required for capturing 5-10 MHz analog bandwidth signals at sufficient oversampling ratio. Its single 3.3V supply simplifies the USB-powered design, and the hardware power-down pin enables the host MCU to idle the converter between trigger events, extending battery life. The -2V to +2V input range covers the conditioned signal from typical front-end attenuator/amplifier chains without external level shifting. Compared to higher-speed ADCs, the THS1230 keeps power consumption low while still meeting the Nyquist criteria for narrowband signal capture.
推荐
Software Defined Radio IF Sampling
The THS1230CDWRG4 supports baseband I/Q digitization in narrowband software-defined radios where the intermediate frequency has been demodulated to within its 0-15 MHz input bandwidth. Its differential input mode is ideal for direct connection to quadrature demodulator outputs (such as an I/Q mixer), rejecting common-mode noise and improving spurious performance. The 30 MSPS throughput provides headroom for digital decimation filtering on the FPGA. The single 3.3V rail aligns with typical RF transceiver supply domains, reducing overall BOM cost compared to ADCs requiring 5V or dual supplies.
推荐
Industrial Machine Vision Camera
Machine vision line-scan and area-scan cameras operating at VGA resolution can leverage the THS1230CDWRG4 for its 30 MSPS throughput and 12-bit pixel depth. The configurable input modes support direct connection to line-scan CCD outputs and CMOS image sensor analog front-ends. The parallel digital bus integrates directly with image processors and FPGA-based vision pipelines. Designers should allocate PCB area for a guard ring around the analog input traces to mitigate digital switching noise from the parallel output bus coupling back into the analog input. Compared to 14- or 16-bit ADCs, the 12-bit resolution cuts system cost while still satisfying most inspection-vision requirements.
推荐
Set-Top Box Video Digitizer
The THS1230CDWRG4 can digitize composite or component analog video streams in legacy set-top box designs that still need to ingest baseband video. Its 30 MSPS sampling rate comfortably exceeds the 27 MHz required for standard-definition video, giving designers margin for digital reconstruction filtering downstream. The configurable input range accepts the typical 1Vpp video signal without external clamping. Compared to dedicated video ADCs, the THS1230 offers a lower-cost general-purpose alternative when broadcast-quality decoding is not required.
推荐
USB-Based Data Acquisition Module
USB-powered bench-top data acquisition modules benefit from the THS1230CDWRG4's low power consumption and single 3.3V supply that can be derived directly from the USB 5V rail via an LDO. The 30 MSPS sample rate supports multi-kHz bandwidth measurements when combined with anti-aliasing filtering, while the 12-bit resolution meets typical laboratory measurement precision. The parallel CMOS output bus interfaces efficiently with USB controller ASICs or FPGAs that aggregate samples for streaming over USB 2.0 or USB 3.0. Compared to audio-bandwidth ADCs, the THS1230 extends useful bandwidth by an order of magnitude, enabling vibration, sonar, and ultrasonic test applications.
推荐
Ultrasound Beamforming Front-End
Low-channel-count ultrasound front-ends for portable or handheld scanners can use the THS1230CDWRG4 to digitize the conditioned transducer signal at 30 MSPS, sufficient for capturing mid-frequency imaging at moderate depth. The configurable single-ended with offset input mode accommodates the bipolar signal returned from the transducer analog front-end. The 12-bit resolution is sufficient for B-mode envelope detection after digital Hilbert transform, and the parallel CMOS outputs feed directly into FPGA beamforming pipelines. Compared to higher-channel-count ultrasound ADCs, the THS1230 is best suited to designs where 1-4 channels are needed.
推荐
推荐产品汇总
工程参考数据： THS1230CDWRG4 ——对比、设计指导和合规信息。
选型指南
与替代料对比
| 参数 | 本产品 | THS1230CDW | THS1230CDWR | THS1230IDW | THS1230IPWG4 | THS1215IPWG4 |
|---|---|---|---|---|---|---|
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments |
| Package | 28-SOIC (DW) | 28-SOIC (DW) | 28-SOIC (DW) | 28-SOIC (DW) | 28-TSSOP (PW) - different | 28-TSSOP (PW) - different |
| Resolution | 12 bit | 12 bit | 12 bit | 12 bit | 12 bit | 12 bit |
| Sample Rate | 30 MSPS | 30 MSPS | 30 MSPS | 30 MSPS | 30 MSPS | 15 MSPS |
| Supply Voltage | 3.3 V | 3.3 V | 3.3 V | 3.3 V | 3.3 V | 3.3 V |
| Operating Temperature | 0 C to +70 C (commercial) | 0 C to +70 C | 0 C to +70 C | -40 C to +85 C (industrial) | -40 C to +85 C (industrial) | -40 C to +85 C (industrial) |
| RoHS / Lead-Free | Yes (G4 suffix) | Non-RoHS (no G4) | Yes (R suffix) | Non-RoHS | Yes (G4) | Yes (G4) |
| Power-Down Mode | Yes | Yes | Yes | Yes | Yes | Yes |
| Output Interface | Parallel CMOS | Parallel CMOS | Parallel CMOS | Parallel CMOS | Parallel CMOS | Parallel CMOS |
关键差异点
- Same die as THS1230CDW but with RoHS-compliant lead-free finish （对比 THS1230CDW)
- Broader temperature range than commercial-grade THS1230CDWRG4 （对比 THS1230IDW)
- Same SOIC-28 footprint across commercial and industrial grades （对比 THS1230IPWG4)
设计说明
Decouple AVDD and DVDD separately with a 10uF bulk ceramic plus a 100nF X7R placed within 5 mm of each supply pin. The THS1230CDWRG4 derives internal references from AVDD; ripple on this rail directly couples into the analog input path, degrading SNR. Designers should isolate AVDD from noisy digital supplies via a ferrite bead or dedicated LDO, especially when the 3.3V rail is shared with an FPGA or switching converter.
Route the 12-bit parallel CMOS output bus with matched trace lengths (within 5 mm of the longest trace) and keep them on the opposite side of the ground plane from the analog input traces. Maintain a continuous analog ground plane under the AINP/AINN traces and reference pins to prevent digital switching noise from coupling back into the analog front-end. Place the REFP/REFN/REFT/REFB reference decoupling capacitors as close as possible to their respective pins.
Driving the CLK input with a noisy or non-monotonic clock source will introduce aperture jitter that limits SNR; use a low-jitter crystal oscillator or FPGA-generated clock with < 10 ps RMS jitter. Avoid leaving the OE pin floating - tie it to DVDD through a 10 kohm resistor if not actively driven, since a floating OE can enable random output toggling and inject switching noise into the analog domain.
When using the differential input mode, keep the AINP and AINN traces symmetric and length-matched to within 1 mm. Route them over a continuous ground plane with no plane splits, since any impedance discontinuity converts common-mode noise into differential-mode error at the ADC input. Source impedance should be matched (typically 50 ohm or 75 ohm termination) to the trace characteristic impedance to minimize reflection-induced distortion at high input frequencies.
The THS1230CDWRG4 dissipates approximately 100-150 mW in active mode (estimated: 3.3 V x typical I_DD based on datasheet functional block), which is well within the SOIC-28 package's thermal budget at room temperature. At maximum ambient of 70 C, the junction temperature remains below 100 C with normal PCB copper area; no special heatsinking is required for commercial-grade applications.
合规信息
RoHS-compliant per G4 suffix designation. Not AEC-Q100 qualified - this part is intended for commercial-grade applications; the THS1230 family does not include an automotive-grade variant. Halogen-free and conflict-mineral status not explicitly stated in available web data.
