EP2SGX130GF40C3N vs EP2SGX130GF40C4NES Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EP2SGX130GF40C3N sa pamamagitan ng Intel at EP2SGX130GF40C4NES sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EP2SGX130GF40C3N EP2SGX130GF40C4NES
Brand Intel Intel
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Huling Pagbili
Family Stratix II GX Stratix II GX
Logic Elements 132,540 132,540
Embedded Memory 6.7 Mbits Approximately 4.5 Mbits (TriMatrix)
Embedded Multipliers (18x18) 252 —
User I/O Count 734 —
Transceiver Count 40 channels —
Max Transceiver Data Rate 6.375 Gbps —
Process Technology 90 nm 90 nm CMOS
Core Voltage 1.2 V 1.2 V
Packhaging 1508-ball FC-FBGA —
Uri ng Pagpapasok Surface Mount (flip-chip BGA) Surface Mount (flip-chip BGA)
Temperature na Operasyon 0C to +85C (commercial) Commercial Extended (per N suffix)
Speed Grade C3 C4 (speed grade -4)
Configuration Mode Passive Serial / Fast Passive Parallel / JTAG —
Tindminan RoHS Compliant —
Logic Blocks / ALMs — Approximately 53,000 ALMs
Maximum Transceiver Data Rate — 6.375 Gbps
Transceiver Channels — Up to 20 (4 to 20, device-dependent)
User I/O Pins — 734
Total Package Pins — 1508 (FC-FBGA ball grid)
Package Code — GF40 (FC-FBGA, 40x40 mm, 1.0 mm pitch)
Internal Operating Frequency — Up to 717 MHz
PLL Blocks — 8
DSP Blocks — Yes (variable, see datasheet)
Lead-Free / RoHS — Yes (LEAD FREE per datasheet family code)
Level ng MSL — Per JEDEC J-STD-020, typically MSL-4 or higher [DATA_NEEDED: exact MSL level]
JEDEC Standard Reference — MS-034AAU-1

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