EP610JI-30 vs EP610LC-35 Comparison
Detailed side-by-side comparison of EP610JI-30 by Altera and EP610LC-35 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP610JI-30 | EP610LC-35 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | NRND | Obsolete |
| Family | Altera Classic EPLD (EP610) | Altera Classic EPLD |
| Device Type | UV Erasable Programmable Logic Device (EPLD) | — |
| Macrocells | 16 | 16 |
| Propagation Delay (tpd) | 30 ns (max) | 37 ns |
| Pipelined Data Rate | Up to 100 MHz | — |
| Product Terms | 160 | — |
| Dedicated Inputs | 4 | — |
| I/O Pins | 16 | — |
| External Clocks | 2 | — |
| Supply Voltage | 5 V (single supply) | — |
| Process Technology | CMOS | — |
| Package | CQCC28 (windowed ceramic JLCC, J-bend) | 28-pin PLCC (J-lead) |
| Package Code | JLCC-28 / CQCC28 | — |
| Erasure Method | Ultraviolet (UV) via top window | — |
| Programming | Altera Logic Programmer compatible | — |
| Operating Temperature | -40C to +85C (industrial, per EP610 family suffix convention) | Commercial (0C to +70C) [DATA_NEEDED: exact grade letter] |
| Mounting Type | Surface Mount (JLCC) | Surface Mount |
| RoHS Status | [DATA_NEEDED: RoHS status - vintage ceramic package, likely non-RoHS] | [DATA_NEEDED: rohs_status] |
| Lead-Free | [DATA_NEEDED: lead-free status] | [DATA_NEEDED: lead_free] |
| Device Series | — | EP610 |
| Usable Gates | — | 300 |
| Supply Voltage (Vcc) | — | 5 V |
| Technology | — | CMOS EEPROM (one-time-programmable plastic) |
| Speed Grade | — | -35 (slowest EP610) |
| Programmable Pins | — | 24 input / 16 output (shared macrocells) |
| MSL Level | — | [DATA_NEEDED: msl_level] |
| Programming Tool | — | MAX+PLUS II development system |