EP610JI-30 vs EP610LC-35 比較
詳細並排比較 EP610JI-30 由 Altera 與 EP610LC-35 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP610JI-30 | EP610LC-35 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | NRND | Obsolete |
| Family | Altera Classic EPLD (EP610) | Altera Classic EPLD |
| Device Type | UV Erasable Programmable Logic Device (EPLD) | — |
| Macrocells | 16 | 16 |
| Propagation Delay (tpd) | 30 ns (max) | 37 ns |
| Pipelined Data Rate | Up to 100 MHz | — |
| Product Terms | 160 | — |
| Dedicated Inputs | 4 | — |
| I/O Pins | 16 | — |
| External Clocks | 2 | — |
| 供應電壓 | 5 V (single supply) | — |
| Process Technology | CMOS | — |
| 封裝 | CQCC28 (windowed ceramic JLCC, J-bend) | 28-pin PLCC (J-lead) |
| Package Code | JLCC-28 / CQCC28 | — |
| Erasure Method | Ultraviolet (UV) via top window | — |
| Programming | Altera Logic Programmer compatible | — |
| 工作溫度 | -40C to +85C (industrial, per EP610 family suffix convention) | Commercial (0C to +70C) [DATA_NEEDED: exact grade letter] |
| 安裝類型 | Surface Mount (JLCC) | Surface Mount |
| RoHS 狀態 | [DATA_NEEDED: RoHS status - vintage ceramic package, likely non-RoHS] | [DATA_NEEDED: rohs_status] |
| Lead-Free | [DATA_NEEDED: lead-free status] | [DATA_NEEDED: lead_free] |
| Device Series | — | EP610 |
| Usable Gates | — | 300 |
| Supply Voltage (Vcc) | — | 5 V |
| Technology | — | CMOS EEPROM (one-time-programmable plastic) |
| Speed Grade | — | -35 (slowest EP610) |
| Programmable Pins | — | 24 input / 16 output (shared macrocells) |
| MSL 等級 | — | [DATA_NEEDED: msl_level] |
| Programming Tool | — | MAX+PLUS II development system |