EPM5192LC-1 vs EPM5192LC-35 Comparison
Detailed side-by-side comparison of EPM5192LC-1 by Altera and EPM5192LC-35 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM5192LC-1 | EPM5192LC-35 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Family | MAX 5000 | MAX 5000 CPLD |
| Device Type | EPLD / CPLD | — |
| Macrocells | 192 | — |
| Logic Gates | 3750 (typical usable) | — |
| Dedicated Inputs | 7 | — |
| User I/O | 64 | — |
| Number of Pins | 84 | — |
| Package Type | LDCC (Leaded Ceramic Chip Carrier), plastic windowless | JLCC (J-Lead Ceramic Chip Carrier) |
| Propagation Delay | 25 ns | — |
| Maximum Clock Frequency | 50 MHz | — |
| Supply Voltage | 5 V nominal (4.75 V to 5.25 V) | — |
| Technology | CMOS, UV-erasable / OTP EPROM cell | — |
| Operating Temperature | 0C to +70C (commercial) | Commercial (0C to +70C) per LC suffix |
| Programmable Memory | EPROM (one-time or UV-erasable) | — |
| Speed Grade | -1 | -35 |
| RoHS Status | Non-compliant (ceramic LDCC with Pb-bearing terminations) | Non-compliant (ceramic hermetic package) |
| Series | — | MAX 5000 |
| Logic Elements / Macrocells | — | 192 macrocells |
| Pin-to-Pin Delay (tPD) | — | 35 ns |
| Programmable Type | — | UV-Erasable / OTP (EPROM-based) |
| Mounting Type | — | Surface Mount |
| Logic Voltage | — | 5 V TTL-compatible I/O |
| Programming Method | — | Altera legacy programmer (EPROM-based) |
| Architecture | — | LAB-based with Programmable Interconnect Array (PIA) |
| I/O Standard | — | TTL |
| Lifecycle Status | — | Obsolete - last-time-buy stock only |
| Datasheet Document | — | Altera MAX 5000 family datasheet (per alldatasheet.com) |