EPM9320LC84-15 vs EPM9320ALC84-20 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM9320LC84-15 sa pamamagitan ng Intel at EPM9320ALC84-20 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPM9320LC84-15 EPM9320ALC84-20
Brand Intel Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete NRND
Family MAX 9000 MAX 9000
Series EPM9320 —
Device Type CPLD (Complex Programmable Logic Device) EPLD (Erasable Programmable Logic Device)
Macrocells 320 320
Usable Gates 6,000 —
Logic Array Blocks (LABs) 20 16
Propagation Delay (tPD) 15 ns (max) —
Maksimum na Taktiko ng Oras 117.6 MHz —
Supply Voltage (VCC) 4.75 V to 5.25 V (5.0 V nominal) —
Programmability 5.0 V in-system programmable (ISP) via JTAG In-system via IEEE 1149.1 JTAG
JTAG Interface IEEE Std. 1149.1 boundary-scan compliant —
Packhaging 84-pin PLCC (Plastic Leaded Chip Carrier) PLCC-84
Uri ng Pagpapasok Surface Mount Surface Mount (PLCC socket compatible)
Temperature na Operasyon -40C to +85C (commercial) [DATA_NEEDED: exact grade] [DATA_NEEDED: commercial or industrial grade]
Technology CMOS EEPROM-based, third-generation Multiple Array MatriX (MAX) —
Built-in Pull-up Resistors Yes, on every I/O pin —
Architecture Feature Pin-locking across design iterations —
Tindminan RoHS [DATA_NEEDED: confirm from manufacturer] [DATA_NEEDED: per Altera datasheet]
Maximum User I/Os — 212
Pin-to-Pin Delay (tPD) — 20 ns
Process Technology — 0.5 µm CMOS EEPROM
Volte ng Pagbibigay — 5.0 V
Configuration Memory — Non-volatile EEPROM
Boundary Scan — JTAG IEEE 1149.1
Design Software — MAX+PLUS II / Quartus II (legacy)

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