IPD30N10S3L34ATMA2 vs IPD30N06S2L13ATMA4 Comparison

Detailed side-by-side comparison of IPD30N10S3L34ATMA2 by Infineon and IPD30N06S2L13ATMA4 by Infineon. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Infineon
IPD30N10S3L34ATMA2 IPD30N10S3L34ATMA2 - 100V 30A N-Ch OptiMOS MOSFET | Infineon

IPD30N10S3L34ATMA2 - 100V 30A N-Ch OptiMOS MOSFET | Infineon

IPD30N10S3L34ATMA2 βœ“ Active
Infineon
IPD30N06S2L13ATMA4 IPD30N06S2L13ATMA4 - 55V 30A N-Channel OptiMOS MOSFET | Infineon

IPD30N06S2L13ATMA4 - 55V 30A N-Channel OptiMOS MOSFET | Infineon

IPD30N06S2L13ATMA4 βœ“ Active

Specification Comparison

Parameter IPD30N10S3L34ATMA2 IPD30N06S2L13ATMA4
Brand Infineon Infineon
Category MOSFETs MOSFETs
Lifecycle Status Active Active
Stock Status In Stock In Stock
Unit Price (USD) $0.92 $0.48
FET Type N-Channel β€”
Drain-Source Voltage (V_DS) 100 V β€”
Continuous Drain Current (I_D, Tc) 30 A β€”
Pulsed Drain Current (I_DM) 180 A β€”
Power Dissipation (P_D, Tc) 57 W β€”
R_DS(on) max at V_GS=10V 31 mOhm (typ) β€”
Gate Threshold Voltage V_GS(th) max 2.4 V β€”
Total Gate Charge (Qg) max 31 nC β€”
Operating Junction Temperature -55 C to +175 C β€”
Package / Supplier Device Package PG-TO252-3-11 (DPAK) β€”
Mounting Type Surface Mount Surface Mount
Pin / Tab Count 3 (2 + Tab) β€”
Technology OptiMOS-T (trench) Planar (OptiMOS)
Automotive Qualification AEC-Q101 AEC-Q101 qualified
MSL Level [DATA_NEEDED: MSL level] β€”
RoHS Status Compliant β€”
Manufacturer β€” Infineon Technologies
Part Family β€” OptiMOS
Channel Type β€” N-Channel
Mode β€” Enhancement
Drain-Source Voltage (Vds) β€” 55 V
Continuous Drain Current (Id) β€” 30 A (Tc)
Power Dissipation (Pd) β€” 136 W (Tc)
Package β€” PG-TO252-3-11 (DPAK)
Operating Temperature β€” -55 Β°C to +175 Β°C (Tj)
MSL (Moisture Sensitivity Level) β€” MSL1 (per JEDEC J-STD-020, up to 260 Β°C peak reflow)
Lead-Free / RoHS β€” Yes (Green Package)
Avalanche Tested β€” 100 % production-tested
On-State Resistance (Rds(on)) β€” [DATA_NEEDED: exact typ/max Rds(on) at Vgs=10V and at Vgs=4.5V]
Gate-Source Threshold (Vgs(th)) β€” Logic-level (typ [DATA_NEEDED: Vth typ/min/max])
Total Gate Charge (Qg) β€” [DATA_NEEDED: Qg @ Vgs=10V, Id=30A]
Input Capacitance (Ciss) β€” [DATA_NEEDED: Ciss typ at Vds=25V]
Diode Reverse Recovery (trr) β€” [DATA_NEEDED: trr typ]
Pin Count β€” 3 (Drain tab + Gate + Source)
Tape and Reel Packaging β€” Yes (T&R per IEC 60286-3)

Datasheets & Resources

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