IPD30N10S3L34ATMA2 - 100V 30A N-Ch OptiMOS MOSFET | Infineon
MPN: IPD30N10S3L34ATMA2 ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $1.85 | $1.85 |
| 10 | $1.62 | $16.20 |
| 100 | $1.38 | $138.00 |
| 500 | $1.18 | $590.00 |
| 1,000 | $1.05 | $1,050.00 |
| 2,500 | $0.92 | $2,300.00 |
Drop-in alternatives for IPD30N10S3L34ATMA2 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
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View Datasheet →IPD30N10S3L34ATMA2 Maximum Ratings & Electrical Characteristics
| FET Type | N-Channel |
| Drain-Source Voltage (V_DS) | 100 V |
| Continuous Drain Current (I_D, Tc) | 30 A |
| Pulsed Drain Current (I_DM) | 180 A |
| Power Dissipation (P_D, Tc) | 57 W |
| R_DS(on) max at V_GS=10V | 31 mOhm (typ) |
| Gate Threshold Voltage V_GS(th) max | 2.4 V |
| Total Gate Charge (Qg) max | 31 nC |
| Operating Junction Temperature | -55 C to +175 C |
| Package / Supplier Device Package | PG-TO252-3-11 (DPAK) |
| Mounting Type | Surface Mount |
| Pin / Tab Count | 3 (2 + Tab) |
| Technology | OptiMOS-T (trench) |
| Automotive Qualification | AEC-Q101 |
| RoHS Status | Compliant |
IPD30N10S3L34ATMA2 Pin Configuration
| Pin 1 | Gate — Gate drive input; 10V V_GS typical for full enhancement |
| Pin 2 | Drain — Drain terminal; internally connected to the mounting tab |
| Pin 3 | Source — Source terminal; reference for gate drive |
| Pin Tab | Drain — Drain tab (electrically tied to Pin 2); main thermal path and high-current terminal |
Safe Operating Area (DC)
Typical Applications
IPD30N10S3L34ATMA2 is suitable for 6 applications: Automotive 12V/24V Load Switching, Electric Power Steering (EPS) Motor Drive, DC-DC Converter High-Side / Low-Side Switch, Battery Management System (BMS) Protection, Industrial Solenoid and Relay Driver, Brushed DC Motor Drive (Automotive and Industrial).
Automotive 12V/24V Load Switching
The IPD30N10S3L34ATMA2's 100 V V_DS rating gives substantial margin above nominal 12 V and 24 V automotive bus rails, tolerating load-dump transients up to 40 V without avalanche breakdown. Its 30 A continuous drain current drives high-current resistive and inductive loads such as headlamp ballasts, seat heaters, and HVAC blowers, while the 31 mOhm R_DS(on) keeps conduction loss under 2.5 W at 9 A typical load. AEC-Q101 qualification and -55 C to +175 C junction range ensure reliability in under-hood environments with thermal cycling and vibration stress.
Recommended
Electric Power Steering (EPS) Motor Drive
In EPS half-bridge and H-bridge configurations, the IPD30N10S3L34ATMA2 switches the brushless DC motor phase windings with low conduction loss and robust body-diode reverse recovery. The 180 A pulsed current rating handles motor start-up and reverse-current spikes, while the 31 nC total gate charge keeps switching loss manageable at 20-50 kHz PWM frequencies typical of EPS controllers. AEC-Q101 qualification matches the stringent automotive safety integrity level (ASIL) requirements for steering subsystems.
Recommended
DC-DC Converter High-Side / Low-Side Switch
The IPD30N10S3L34ATMA2 works as either the high-side or low-side switch in 12 V to 48 V buck and boost converters up to several hundred watts. Its 31 mOhm R_DS(on) at V_GS = 10 V yields low conduction loss, and the 31 nC Qg supports switching frequencies up to 500 kHz, enabling compact inductor and capacitor selection. The PG-TO252-3-11 package provides a thermal pad for direct PCB cooling, which is critical at the 57 W power dissipation rating.
Recommended
Battery Management System (BMS) Protection
In BMS disconnect and pre-charge circuits, the IPD30N10S3L34ATMA2 acts as a low-resistance solid-state switch replacing traditional contactors, with 31 mOhm R_DS(on) keeping continuous current path loss low. The 100 V V_DS handles series-cell battery packs up to 36 V nominal, and AEC-Q101 qualification ensures long-term reliability under the temperature swings of battery enclosures. Its fast switching capability supports pre-charge resistor bypass within milliseconds of contactor-closure detection.
Recommended
Industrial Solenoid and Relay Driver
The IPD30N10S3L34ATMA2 drives 24 V industrial solenoids, pneumatic valves, and mechanical relays with low-side N-channel switching topology. Its 30 A continuous current easily handles the inrush of large solenoids, while the rugged OptiMOS-T body diode clamps inductive kickback without external freewheeling diodes in many cases. The PG-TO252-3-11 package's tab connection provides both thermal relief and a low-inductance source-return path for fast switching edges.
Recommended
Brushed DC Motor Drive (Automotive and Industrial)
For brushed DC motor H-bridges driving window lifts, seat adjusters, fans, pumps, and small industrial drives, the IPD30N10S3L34ATMA2 provides the per-leg switching element with robust avalanche energy absorption. The 180 A pulsed current handles motor stall conditions, while the 31 mOhm R_DS(on) keeps bridge dissipation low for thermal-conscious PCB layouts. The DPAK footprint allows compact bridge designs with all four FETs on a single thermal copper pour, simplifying thermal management.
Recommended
Recommended Products Summary
Engineering reference data for IPD30N10S3L34ATMA2 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | IPD30N10S3L34ATMA1 | IPD70N10S312ATMA2 | IPD33CN10NGATMA1 | IPD90N06S407ATMA2 |
|---|---|---|---|---|---|
| Package | PG-TO252-3-11 (DPAK) | PG-TO252-3-11 (DPAK) - same | PG-TO252-3-11 (DPAK) - same | PG-TO252-3-11 (DPAK) - same | PG-TO252-3-11 (DPAK) - same |
| Brand | Infineon | Infineon - same | Infineon - same | Infineon - same | Infineon - same |
| V_DS max (V) | 100 V | 100 V | 100 V | 100 V | 60 V |
| Continuous I_D (A) | 30 A | 30 A | 70 A | 33 A | 90 A |
| R_DS(on) typ at 10V (mOhm) | 31 mOhm | 31 mOhm | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] |
| Total Gate Charge Qg max (nC) | 31 nC | 31 nC | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] |
| Automotive Grade | AEC-Q101 | AEC-Q101 | AEC-Q101 | AEC-Q101 | AEC-Q101 |
| Technology | OptiMOS-T (trench) | OptiMOS-T | OptiMOS | OptiMOS | OptiMOS |
| Unit Price @ 1k (USD, as of 2026-09-13) | 1.05 | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] |
Key Differentiators
- Original ATMA2 packing revision with confirmed availability (vs IPD30N10S3L34ATMA1)
- OptiMOS-T technology with industry-leading FOM (vs IPD70N10S312ATMA2)
- AEC-Q101 qualified with extended temperature range (vs IPD90N06S407ATMA2)
Design Notes
Estimated: at I_D = 30 A continuous and R_DS(on) = 31 mOhm, conduction loss is approximately 28 W, exceeding the 57 W P_D rating only at elevated Tc. The PG-TO252-3-11 (DPAK) tab must be soldered to a copper pour of at least 1 square inch (645 mm^2) on a 2 oz copper layer to achieve theta_JA below 50 C/W. Without active cooling, expect practical continuous current ceiling of 15-20 A. Use multiple thermal vias under the tab to spread heat into inner copper planes.
Layout the gate-drive loop (gate resistor -> gate pin -> source pin -> gate-driver ground) as small as physically possible, ideally under 1 nH loop inductance, to prevent gate-rail ringing and dv/dt-induced Miller turn-on. Place a 10-100 kOhm gate-source resistor directly at the gate pin to ensure the MOSFET stays off during controller power-up. Use a 4-layer PCB with a dedicated ground plane below the switching node to minimize parasitic inductance on the drain-source loop.
Do not exceed V_GS = +/-20 V absolute maximum; gate-source ESD damage is a common failure mode when the gate is left floating during handling or hot-plug events. Ensure the gate-drive voltage reaches at least 10 V for full enhancement; partial enhancement at V_GS = 4-6 V dramatically increases R_DS(on) and can cause thermal runaway. For high-side N-channel switching, include a bootstrap or charge-pump supply because the source pin voltage rises above ground when the FET is on.
Keep the switching-node copper area minimal to reduce radiated EMI; however, provide adequate copper for current handling (1 oz copper handles roughly 1 A per mm of trace width with 10 C temperature rise). For half-bridge layouts, interleave high-side and low-side FET drains with a shared thermal copper pour, but keep gate traces separated to avoid cross-conduction. Place bulk input capacitors within 5 mm of the high-side drain to minimize parasitic inductance that causes voltage spikes during switching transitions.
Compliance Information
AEC-Q101 (automotive) qualified per Infineon product page; RoHS and REACH compliant; MSL level not stated in the verified data and is marked [DATA_NEEDED] in specs.
