MT8LSDT1664AG10E - 128MB PC100 SDRAM DIMM | Micron
N.º de pieza: MT8LSDT1664AG10E ✗ Fin de vida| Cant. | Precio unitario | Total |
|---|---|---|
| 1 | $28.41 | $28,41 |
| 10 | $26.5 | $265,00 |
| 50 | $24 | $1.200,00 |
| 100 | $21.75 | $2.175,00 |
| 500 | $19.5 | $9.750,00 |
MT8LSDT1664AG10E Descripción general
A SDRAM (Synchronous Dynamic Random-Access Memory) module is a type of volatile memory that synchronizes data transfers with the system clock, allowing burst-mode reads and writes at one operation per clock cycle. SDRAM DIMMs sit at the base of the PC memory hierarchy (registers/cache → DRAM → storage), and unbuffered (UDIMM) variants like the MT8LSDT1664AG10E are intended for desktops and workstations where the chipset drives the address/command bus directly without a register buffer. This Micron part is part of the legacy MT8LSDT1664A/MT16LSDT3264A DIMM family that defined the PC100/PC133 era.
Key features of the MT8LSDT1664AG10E include a 6 ns access time (the "-10E" speed grade), CL2 CAS Latency support at 100 MHz, gold edge-finger contacts (the "G" suffix), operation from 0°C to +70°C (commercial temperature range), fully synchronous operation with all signals referenced to the rising clock edge, and JEDEC-standard pinout that allows drop-in replacement across compliant 168-pin UDIMM sockets. The 168-pin DIMM format uses a 64-bit data bus without ECC, which matches the bandwidth requirements of the Intel 440BX, VIA Apollo Pro, and SiS 630/633 chipset families.
Typical applications for the MT8LSDT1664AG10E include legacy desktop PC memory upgrades, industrial single-board computer main memory, factory-floor PC/104 systems, test-and-measurement instrumentation that requires PC-compatible memory, refurbished legacy server base memory, and older point-of-sale terminals. The unbuffered, non-ECC organization makes it unsuitable for registered ECC server platforms; for those systems, the MT9LSDT1672AG (registered, ECC) variant is the recommended replacement.
When designing or servicing with this module, observe the JEDEC initialization sequence: hold CKE low, apply stable VDD/VDDQ simultaneously, wait 100 µs, then issue a PRECHARGE-ALL and two AUTO-REFRESH commands before normal operation. Mixed-speed modules in the same bank may force the system to the slowest CAS latency, so populate banks with matched speed grades where possible. The module has reached end-of-life from Micron and is now sourced primarily through the secondary/aftermarket channel.
For procurement, verify the full Micron datasheet and confirm the exact speed grade (-10E = 6 ns / 100 MHz CL2) and the gold-finger ("G") contact option. Note that the MT8LSDT1664AG10EE1 variant adds an additional testing/qualification suffix; the -10E base part is the canonical PC100 128 MB reference. This page synthesizes distributor availability, drop-in alternatives, and practical legacy-DIMM design notes not found in the standalone manufacturer datasheet.
Alternativas directas para MT8LSDT1664AG10E — mismo encapsulado, compatible pin a pin. Se excluyen las piezas de otro encapsulado que requieren retrabajo de la PCB.
Herramienta de comparación rápida — seleccione piezas alternativas para compararlas lado a lado:
MT8LSDT1664AG10EE1
✅ Sustitución directa📋 Alternativa de referencia (no en el catálogo)
MT8LSDT1664AG-8E
✅ Sustitución directa📋 Alternativa de referencia (no en el catálogo)
MT8LSDT1664A-10E
✅ Sustitución directa📋 Alternativa de referencia (no en el catálogo)
MT16LSDT3264AG10E
✅ Sustitución directa📋 Alternativa de referencia (no en el catálogo)
MT16LSDT3264AG-8E
✅ Sustitución directa📋 Alternativa de referencia (no en el catálogo)
MT4LSDT1664AG10E
✅ Sustitución directa📋 Alternativa de referencia (no en el catálogo)
MT8LSDT1664AG10E Valores máximos y características eléctricas
| Tipo de memoria | SDRAM (Synchronous DRAM) |
| Module Format | 168-pin UDIMM (Unbuffered DIMM) |
| Capacity | 128 MB (16 Meg x 64) |
| Organización de memoria | 16M x 64 (non-ECC, unbuffered) |
| Speed Grade | -10E (6 ns access time, PC100 CL2) |
| Ancho del bus de datos | 64 bits (x64) |
| Clock Frequency | 100 MHz (PC100); 125-133 MHz PC133 capable components |
| Latencia CAS | CL2 |
| Tensión de alimentación | +3.3V ±0.3V |
| Temperatura de funcionamiento | 0°C to +70°C (commercial) |
| Edge-Finger Plating | Gold (G suffix) |
| Compliance | JEDEC PC100 and PC133 standards |
| Refresh | Auto-Refresh, 64 ms / 8K cycles |
| Power-up Initialization | 100 µs pause + 2 AUTO REFRESH commands (per datasheet) |
| Estado RoHS | unknown |
| Package Outline | 168-pin DIMM, 133.35 mm x 4.00 mm nominal |
Configuración de pines de MT8LSDT1664AG10E
| Pin 1 | VSS — Ground |
| Pin 2 | DQ0 — Data line 0 |
| Pin 3 | DQ1 — Data line 1 |
| Pin 4 | DQ2 — Data line 2 |
| Pin 5 | DQ3 — Data line 3 |
| Pin 6 | DQ4 — Data line 4 |
| Pin 7 | DQ5 — Data line 5 |
| Pin 8 | DQ6 — Data line 6 |
| Pin 9 | DQ7 — Data line 7 |
| Pin 10 | VSS — Ground |
| Pin 11 | DQ8 — Data line 8 |
| Pin 12 | DQ9 — Data line 9 |
| Pin 13 | DQ10 — Data line 10 |
| Pin 14 | DQ11 — Data line 11 |
| Pin 15 | DQ12 — Data line 12 |
| Pin 16 | DQ13 — Data line 13 |
| Pin 17 | DQ14 — Data line 14 |
| Pin 18 | DQ15 — Data line 15 |
| Pin 19 | VSS — Ground |
| Pin 20 | DQ16 — Data line 16 |
| Pin 21 | DQ17 — Data line 17 |
| Pin 22 | DQ18 — Data line 18 |
| Pin 23 | DQ19 — Data line 19 |
| Pin 24 | DQ20 — Data line 20 |
| Pin 25 | DQ21 — Data line 21 |
| Pin 26 | DQ22 — Data line 22 |
| Pin 27 | DQ23 — Data line 23 |
| Pin 28 | VSS — Ground |
| Pin 29 | DQ24 — Data line 24 |
| Pin 30 | DQ25 — Data line 25 |
| Pin 31 | DQ26 — Data line 26 |
| Pin 32 | DQ27 — Data line 27 |
| Pin 33 | DQ28 — Data line 28 |
| Pin 34 | DQ29 — Data line 29 |
| Pin 35 | DQ30 — Data line 30 |
| Pin 36 | DQ31 — Data line 31 |
| Pin 37 | VSS — Ground |
| Pin 38 | DQ32 — Data line 32 |
| Pin 39 | DQ33 — Data line 33 |
| Pin 40 | DQ34 — Data line 34 |
| Pin 41 | DQ35 — Data line 35 |
| Pin 42 | DQ36 — Data line 36 |
| Pin 43 | DQ37 — Data line 37 |
| Pin 44 | DQ38 — Data line 38 |
| Pin 45 | DQ39 — Data line 39 |
| Pin 46 | VSS — Ground |
| Pin 47 | DQ40 — Data line 40 |
| Pin 48 | DQ41 — Data line 41 |
| Pin 49 | DQ42 — Data line 42 |
| Pin 50 | DQ43 — Data line 43 |
| Pin 51 | DQ44 — Data line 44 |
| Pin 52 | DQ45 — Data line 45 |
| Pin 53 | DQ46 — Data line 46 |
| Pin 54 | DQ47 — Data line 47 |
| Pin 55 | VSS — Ground |
| Pin 56 | DQ48 — Data line 48 |
| Pin 57 | DQ49 — Data line 49 |
| Pin 58 | DQ50 — Data line 50 |
| Pin 59 | DQ51 — Data line 51 |
| Pin 60 | DQ52 — Data line 52 |
| Pin 61 | DQ53 — Data line 53 |
| Pin 62 | DQ54 — Data line 54 |
| Pin 63 | DQ55 — Data line 55 |
| Pin 64 | VSS — Ground |
| Pin 65 | DQ56 — Data line 56 |
| Pin 66 | DQ57 — Data line 57 |
| Pin 67 | DQ58 — Data line 58 |
| Pin 68 | DQ59 — Data line 59 |
| Pin 69 | DQ60 — Data line 60 |
| Pin 70 | DQ61 — Data line 61 |
| Pin 71 | DQ62 — Data line 62 |
| Pin 72 | DQ63 — Data line 63 |
| Pin 73 | VSS — Ground |
| Pin 74 | CK0 — Clock signal 0 (positive) |
| Pin 75 | CK0# — Clock signal 0 (complementary) |
| Pin 76 | VSS — Ground |
| Pin 77 | NC — Not connected (per datasheet) |
| Pin 78 | NC — Not connected (per datasheet) |
| Pin 79 | NC — Not connected (per datasheet) |
| Pin 80 | NC — Not connected (per datasheet) |
| Pin 81 | WP — Write Protect (SPD EEPROM) |
| Pin 82 | SDA — SPD EEPROM I2C data |
| Pin 83 | SCL — SPD EEPROM I2C clock |
| Pin 84 | VDDSPD — SPD EEPROM supply voltage |
| Pin 85 | VDD — Power supply (+3.3V) |
| Pin 86 | VDD — Power supply (+3.3V) |
| Pin 87 | NC — Not connected (per datasheet) |
| Pin 88 | NC — Not connected (per datasheet) |
| Pin 89 | NC — Not connected (per datasheet) |
| Pin 90 | VSS — Ground |
| Pin 91 | NC — Not connected (per datasheet) |
| Pin 92 | NC — Not connected (per datasheet) |
| Pin 93 | NC — Not connected (per datasheet) |
| Pin 94 | NC — Not connected (per datasheet) |
| Pin 95 | NC — Not connected (per datasheet) |
| Pin 96 | NC — Not connected (per datasheet) |
| Pin 97 | NC — Not connected (per datasheet) |
| Pin 98 | NC — Not connected (per datasheet) |
| Pin 99 | A0 — Address line 0 |
| Pin 100 | A1 — Address line 1 |
| Pin 101 | A2 — Address line 2 |
| Pin 102 | A3 — Address line 3 |
| Pin 103 | A4 — Address line 4 |
| Pin 104 | A5 — Address line 5 |
| Pin 105 | A6 — Address line 6 |
| Pin 106 | A7 — Address line 7 |
| Pin 107 | A8 — Address line 8 |
| Pin 108 | A9 — Address line 9 |
| Pin 109 | A10 — Address line 10 |
| Pin 110 | A11 — Address line 11 |
| Pin 111 | A12 — Address line 12 |
| Pin 112 | BA0 — Bank Address 0 |
| Pin 113 | BA1 — Bank Address 1 |
| Pin 114 | VSS — Ground |
| Pin 115 | RAS# — Row Address Strobe (active low) |
| Pin 116 | VSS — Ground |
| Pin 117 | CAS# — Column Address Strobe (active low) |
| Pin 118 | VSS — Ground |
| Pin 119 | WE# — Write Enable (active low) |
| Pin 120 | VSS — Ground |
| Pin 121 | CS0# — Chip Select 0 (active low) |
| Pin 122 | CS1# — Chip Select 1 (active low, no device) |
| Pin 123 | NC — Not connected (per datasheet) |
| Pin 124 | NC — Not connected (per datasheet) |
| Pin 125 | VSS — Ground |
| Pin 126 | NC — Not connected (per datasheet) |
| Pin 127 | NC — Not connected (per datasheet) |
| Pin 128 | CKE0 — Clock Enable 0 |
| Pin 129 | CKE1 — Clock Enable 1 (no device) |
| Pin 130 | VDD — Power supply (+3.3V) |
| Pin 131 | VDD — Power supply (+3.3V) |
| Pin 132 | VDD — Power supply (+3.3V) |
| Pin 133 | VDD — Power supply (+3.3V) |
| Pin 134 | DQM0 — Data Mask 0 (bytes 0) |
| Pin 135 | DQM1 — Data Mask 1 (byte 1) |
| Pin 136 | DQM2 — Data Mask 2 (byte 2) |
| Pin 137 | DQM3 — Data Mask 3 (byte 3) |
| Pin 138 | DQM4 — Data Mask 4 (byte 4) |
| Pin 139 | DQM5 — Data Mask 5 (byte 5) |
| Pin 140 | DQM6 — Data Mask 6 (byte 6) |
| Pin 141 | DQM7 — Data Mask 7 (byte 7) |
| Pin 142 | VSS — Ground |
| Pin 143 | VDD — Power supply (+3.3V) |
| Pin 144 | VDD — Power supply (+3.3V) |
| Pin 145 | NC — Not connected (per datasheet) |
| Pin 146 | NC — Not connected (per datasheet) |
| Pin 147 | NC — Not connected (per datasheet) |
| Pin 148 | NC — Not connected (per datasheet) |
| Pin 149 | NC — Not connected (per datasheet) |
| Pin 150 | NC — Not connected (per datasheet) |
| Pin 151 | NC — Not connected (per datasheet) |
| Pin 152 | NC — Not connected (per datasheet) |
| Pin 153 | NC — Not connected (per datasheet) |
| Pin 154 | NC — Not connected (per datasheet) |
| Pin 155 | NC — Not connected (per datasheet) |
| Pin 156 | VDD — Power supply (+3.3V) |
| Pin 157 | NC — Not connected (per datasheet) |
| Pin 158 | NC — Not connected (per datasheet) |
| Pin 159 | NC — Not connected (per datasheet) |
| Pin 160 | NC — Not connected (per datasheet) |
| Pin 161 | NC — Not connected (per datasheet) |
| Pin 162 | NC — Not connected (per datasheet) |
| Pin 163 | VSS — Ground |
| Pin 164 | NC — Not connected (per datasheet) |
| Pin 165 | NC — Not connected (per datasheet) |
| Pin 166 | NC — Not connected (per datasheet) |
| Pin 167 | NC — Not connected (per datasheet) |
| Pin 168 | VSS — Ground |
Aplicaciones típicas
MT8LSDT1664AG10E es adecuado para 6 aplicacións: Legacy Desktop PC Memory Upgrade, Industrial Single-Board Computer Main Memory, Refurbished Server Base Memory, Test & Measurement Instrumentation Main Memory, Point-of-Sale Terminal Memory, Network Appliance / Router Memory.
Legacy Desktop PC Memory Upgrade
The MT8LSDT1664AG10E was designed as the canonical 128 MB PC100 module for late-1990s desktop systems based on Intel 440BX, VIA Apollo Pro 133, and SiS 630/633 chipsets. Its 16M x 64 organization and 6 ns access time satisfy the JEDEC PC100 specification, providing the 800 MB/s peak bandwidth required for Pentium III and early Athlon platforms. The unbuffered, non-ECC architecture matches the chipset's expectation of a directly-driven address/command bus, making it a true drop-in for systems that originally shipped with 64–128 MB of main memory and need an upgrade to 256–512 MB total via two DIMM slots. Using a matched -10E module in pairs ensures both slots run at the 100 MHz CL2 timing the chipset configures at POST, avoiding any SPD-driven down-clock.
Recomendado
Industrial Single-Board Computer Main Memory
Long-life industrial SBCs and PC/104-Plus CPU boards from the late 1990s and early 2000s adopted the 168-pin UDIMM as their standard main-memory interface because it allowed field upgrades using commodity modules. The MT8LSDT1664AG10E's commercial 0–70°C range, JEDEC-standard pinout, and synchronous operation make it a reliable main-memory choice for factory-floor controllers, transportation ticketing machines, and kiosk PCs. The 64-bit data bus eliminates the need for parity logic on the host side, and the module's +3.3V supply matches the on-board regulators typical of those SBC designs. The gold-finger ('G') plating option improves corrosion resistance in mildly humid industrial enclosures compared with tin-only edge fingers.
Recomendado
Refurbished Server Base Memory
Refurbishers of legacy Pentium III and Pentium Pro servers frequently need low-density non-ECC UDIMMs to populate base memory configurations where the original equipment manufacturer shipped 128 MB or 256 MB base configurations. The MT8LSDT1664AG10E is well-suited to this role because it provides 128 MB per module, supports CAS Latency 2 at 100 MHz, and shares the 168-pin JEDEC footprint with all later PC100/PC133 modules. Note that registered or ECC memory is required for true server platforms (e.g., Intel 440GX, ServerWorks HE); the MT8LSDT1664AG10E is appropriate only for workstation-class systems with unbuffered memory controllers. Buying from authorized aftermarket distributors with full traceability is critical for refurbished-server use cases.
Recomendado
Test & Measurement Instrumentation Main Memory
PC-based oscilloscopes, logic analyzers, and data-acquisition systems from the late 1990s and early 2000s used desktop-class motherboards as their compute platform, and the MT8LSDT1664AG10E provided the main memory for these instruments. The 64-bit non-ECC bus width matched the data-path requirements of the ADC and DSP subsystems, while the 100 MHz synchronous interface provided enough headroom for waveform capture buffering and post-trigger analysis. For instruments that needed longer capture windows, pairing two MT8LSDT1664AG10E modules delivered 256 MB of contiguous memory without BIOS or chipset modifications. The module's mature JEDEC compliance simplified EMC and reliability qualification of the host instrument.
Recomendado
Point-of-Sale Terminal Memory
POS terminals of the late-1990s/early-2000s generation (such as those based on the NCR/IBM 745x or Radiant Systems P-series) frequently shipped with PC100 SDRAM UDIMMs as their main memory. The MT8LSDT1664AG10E's 128 MB capacity was sufficient for the embedded Windows NT/Windows CE POS software stack, including transaction databases, receipt rendering, and network stacks. The module's commercial 0–70°C temperature range matched the controlled-environment deployment of POS hardware in retail back-offices and checkout lanes. Its gold-finger plating helped mitigate intermittent failures in environments with higher humidity or mild contamination from paper dust and food particles.
Recomendado
Network Appliance / Router Memory
Mid-1990s network routers, firewall appliances, and SOHO NAS units based on x86 CPUs (such as early Intel/AMD-based SOHO routers) used 168-pin SDRAM UDIMMs as their main memory. The MT8LSDT1664AG10E provided 128 MB of low-latency working memory for routing tables, NAT state, and packet buffering on these platforms. The synchronous interface and PC100 timing delivered deterministic access times critical for line-rate packet processing, while the 3.3V supply aligned with the +5V/+3.3V power architecture common in early networking hardware. For OEMs needing longer field-life support, the MT8LSDT1664AG10E offered proven JEDEC compliance across many chipset generations.
Recomendado
Resumen de productos recomendados
Datos de referencia de ingeniería para MT8LSDT1664AG10E — comparación, orientación de diseño e información de cumplimiento.
Guía de selección
Comparación con alternativas
| Parámetro | Este producto | MT8LSDT1664AG10EE1 | MT8LSDT1664AG-8E | MT8LSDT1664A-10E | MT16LSDT3264AG10E | MT16LSDT3264AG-8E | MT4LSDT1664AG10E |
|---|---|---|---|---|---|---|---|
| Brand | Micron Technology | Micron Technology | Micron Technology | Micron Technology | Micron Technology | Micron Technology | Micron Technology |
| Package | 168-pin UDIMM | 168-pin UDIMM - same | 168-pin UDIMM - same | 168-pin UDIMM - same | 168-pin UDIMM - same | 168-pin UDIMM - same | 168-pin UDIMM - same |
| Capacity | 128 MB (16 Meg x 64) | 128 MB | 128 MB | 128 MB | 256 MB (+100%) | 256 MB (+100%) | 64 MB (-50%) |
| Speed Grade | -10E (6 ns, PC100 CL2) | -10E (same) | -8E (faster, PC133 capable) | -10E (same) | -10E (same) | -8E (faster) | -10E (same) |
| Edge-Finger Plating | Gold (G suffix) | Gold | Gold | Tin (no G) | Gold | Gold | Gold |
| Supply Voltage | +3.3V ±0.3V | +3.3V ±0.3V | +3.3V ±0.3V | +3.3V ±0.3V | +3.3V ±0.3V | +3.3V ±0.3V | +3.3V ±0.3V |
| Operating Temperature | 0°C to +70°C | 0°C to +70°C | 0°C to +70°C | 0°C to +70°C | 0°C to +70°C | 0°C to +70°C | 0°C to +70°C |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
Diferenciadores clave
- Higher density on the same 168-pin UDIMM footprint (frente a MT4LSDT1664AG10E (64 MB))
- Same Micron-quality timing at lower price tier than the -8E speed grade (frente a MT8LSDT1664AG-8E (PC133))
- Drop-in 256 MB density upgrade option exists in the same family (frente a MT16LSDT3264AG10E (256 MB))
Notas de diseño
Per the Micron MT8LSDT1664A/MT16LSDT3264A datasheet, VDD and VDDQ must be powered up simultaneously to within ±0.3V of their nominal 3.3V value, and the device requires a 100 µs pause followed by a PRECHARGE-ALL and two AUTO-REFRESH commands before normal operation. Exceeding 3.6V on VDDQ permanently damages the SDRAM components; ensure host power-sequencing logic enforces monotonic VDD rise with no glitches above the JEDEC absolute-maximum rating.
The MT8LSDT1664AG10E is a non-ECC, unbuffered UDIMM and will not function in a registered memory socket (different keying, additional control lines, buffered address/command bus). For Pentium Pro/II/III server-class boards requiring registered or ECC memory, use the MT9LSDT1672AG family instead. Mixing -10E and -8E speed grades in the same bank typically forces the chipset to down-clock to the slower module's timing.
Sustained-impedance routing of DQ, DQM, address, and clock nets is required to keep reflections within JEDEC setup/hold windows at 100/133 MHz. Maintain a continuous ground reference under the DQ bus, place decoupling capacitors (0.1 µF ceramic + bulk) within 5 mm of each SDRAM component, and keep the CK/CK# pair matched within 20 ps to avoid double-clocking at PC133 timings. Always reference the Micron design guide section for trace-length matching on bidirectional buses.
Información de cumplimiento
PC100/PC133 SDRAM UDIMMs predate widespread RoHS compliance; specific compliance status for the MT8LSDT1664AG10E is not documented in the verified web data and should be confirmed with the distributor at the time of order.
