Altera

EPM3256ATC144-10AA - MAX 3000A CPLD, 256 Macrocells, 10ns TQFP-144 | Altera

Référence : EPM3256ATC144-10AA ✗ Fin de vie

En stock Expédié sous 1 à 3 jours ouvrés

3.3 V Vdss 144-pin TQFP Package 95.2 MHz Speed

À partir de $11.6 USD / unité

MOQ : 1 |

Prix mis à jour : 2026-09-12

Tarifs dégressifs

Qté	Prix unitaire	Total
1	$22.5	$22,50
10	$19.8	$198,00
100	$16.4	$1 640,00
500	$13.95	$6 975,00
1 000	$11.6	$11 600,00

ℹ️ Tous les prix sont en USD

Voir la fiche technique (PDF) Voir les alternatives

Quantité

EPM3256ATC144-10AA Présentation

The Altera EPM3256ATC144-10AA is a member of the MAX 3000A Complex Programmable Logic Device (CPLD) family, delivering 256 macrocells, 5,000 usable gates, and a 10 ns pin-to-pin propagation delay in a 144-pin TQFP package. This commercial-temperature device operates from a 3.3 V core supply and supports 2.5 V, 3.3 V, or 5.0 V I/O operation through the multi-voltage VCCIO pins, enabling mixed-voltage interfacing without external level shifters.

A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that combines multiple PAL-like macrocell blocks on a single chip with a central interconnect. Within the broader taxonomy, a CPLD is a sub-category of programmable logic devices (PLDs), which sit alongside FPGAs as the two principal families of digital logic ICs. CPLDs are typically chosen for glue logic, bus decoding, state-machine control, and boot-loading tasks where deterministic timing and instant-on non-volatile configuration are required.

Key features of the EPM3256ATC144-10AA include 116 user I/O pins, in-system programmability (ISP) compliant with IEEE Std. 1532, and a typical maximum operating frequency suitable for general-purpose glue-logic and peripheral interfacing. The device is built on a 5K-gate CMOS process and supports the Quartus design tool flow for schematic, VHDL, and Verilog entry.

Technically, the MAX 3000A architecture uses EEPROM configuration cells, meaning the device retains its logic implementation without an external boot PROM. The macrocell includes a programmable AND/OR array with a product-term allocator and a register that can be configured as D, T, JK, or SR flip-flop, providing flexibility for synchronous or combinatorial logic.

Typical applications include bus-interface bridging (e.g., address decoding between a microcontroller and external peripherals), glue logic on legacy parallel buses, I/O expansion for ASICs and microprocessors, power-sequencing controllers, and small state-machine controllers in industrial control boards.

When designing with this part, ensure that all VCCIO banks are powered before configuration begins and that JTAG pins (TCK, TMS, TDI, TDO) are properly pulled to avoid spurious configuration. Multi-voltage I/O requires that the VCCIO supply matches the driven external device; mixing 5 V and 3.3 V signals requires separate VCCIO banks.

This page synthesizes distributor pricing, drop-in same-family alternatives, and practical design notes not consolidated in the manufacturer datasheet, giving engineers a single reference for sourcing and substitution decisions.

Alternatives de remplacement direct pour EPM3256ATC144-10AA — même boîtier, compatible broche à broche. Les références à boîtier différent nécessitant une retouche du PCB sont exclues.

Variantes de cette série

Modèles de la même série directement compatibles avec EPM3256ATC144-10AA (même facteur de forme et même empreinte) — différant par Package, Operating Temperature, JTAG Support, Device Type, Propagation Delay (tPD).

EPM3256ATC144-10

Intel

Package: 144-pin TQFP (20x20 mm)

Operating Temperature: 0 C to +70 C (Commercial)