EPM5128GI - 128-Cell UV PLD, MAX 5000, CPGA-68 | Altera
MPN: EPM5128GI β End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $38.5 | $38.50 |
| 10 | $32.75 | $327.50 |
| 100 | $27.4 | $2,740.00 |
| 500 | $23.1 | $11,550.00 |
| 1,000 | $19.85 | $19,850.00 |
Drop-in alternatives for EPM5128GI β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
EPM5128GC
β Drop-Inβ In Stock
$19.2 / Unit
View Datasheet βEPM5128GC-1
β Drop-Inβ In Stock
$18.95 / Unit
View Datasheet βEPM5128GC-2
β Drop-Inβ In Stock
$8.95 / Unit
View Datasheet βEPM5128GC2
β Drop-Inβ In Stock
$54 / Unit
View Datasheet βEPM5128GI-1
β Drop-Inπ Reference alternative (not in catalog)
EPM5128GI Maximum Ratings & Electrical Characteristics
| Product Type | CPLD (Complex Programmable Logic Device) |
| Family | MAX 5000 |
| Logic Cells / Macrocells | 128 |
| Propagation Delay (tPD) | 55 ns |
| Supply Voltage | 5 V |
| Technology | CMOS, UV-erasable EPROM |
| Package | CPGA-68 (Ceramic Pin Grid Array, windowed) |
| Pin Count | 68 |
| Mounting Type | Through-hole (socketed PGA) |
| Operating Temperature Grade | Industrial |
| Programmability | UV-erasable (windowed), field-programmable |
| Configuration Memory | Non-volatile EPROM (no external boot device) |
| Manufacturer | Altera Corporation (now Intel PSG) |
| Lifecycle Status | Obsolete (last produced by Altera, legacy stock via distributors) |
EPM5128GI Pin Configuration
| Pin 1 | I/O β User I/O pin (bidirectional, programmable) |
| Pin 2 | I/O β User I/O pin (bidirectional, programmable) |
| Pin 3 | I/O β User I/O pin (bidirectional, programmable) |
| Pin 4 | I/O β User I/O pin (bidirectional, programmable) |
| Pin 5 | I/O β User I/O pin (bidirectional, programmable) |
| Pin 6 | I/O β User I/O pin (bidirectional, programmable) |
| Pin 7 | I/O β User I/O pin (bidirectional, programmable) |
| Pin 8 | GND β Ground |
| Pin 9 | I/O β User I/O pin (bidirectional, programmable) |
| Pin 10 | I/O β User I/O pin (bidirectional, programmable) |
| Pin 11 | I/O β User I/O pin (bidirectional, programmable) |
| Pin 12 | I/O β User I/O pin (bidirectional, programmable) |
| Pin 13 | I/O β User I/O pin (bidirectional, programmable) |
| Pin 14 | I/O β User I/O pin (bidirectional, programmable) |
| Pin 15 | I/O β User I/O pin (bidirectional, programmable) |
| Pin 16 | I/O β User I/O pin (bidirectional, programmable) |
| Pin 17 | I/O β User I/O pin (bidirectional, programmable) |
| Pin 18 | I/O β User I/O pin (bidirectional, programmable) |
| Pin 19 | I/O β User I/O pin (bidirectional, programmable) |
| Pin 20 | GND β Ground |
| Pin 21 | I/O β User I/O pin (bidirectional, programmable) |
| Pin 22 | I/O β User I/O pin (bidirectional, programmable) |
| Pin 23 | I/O β User I/O pin (bidirectional, programmable) |
| Pin 24 | I/O β User I/O pin (bidirectional, programmable) |
| Pin 25 | I/O β User I/O pin (bidirectional, programmable) |
| Pin 26 | I/O β User I/O pin (bidirectional, programmable) |
| Pin 27 | I/O β User I/O pin (bidirectional, programmable) |
| Pin 28 | I/O β User I/O pin (bidirectional, programmable) |
| Pin 29 | I/O β User I/O pin (bidirectional, programmable) |
| Pin 30 | GND β Ground |
| Pin 31 | I/O β User I/O pin (bidirectional, programmable) |
| Pin 32 | I/O β User I/O pin (bidirectional, programmable) |
| Pin 33 | I/O β User I/O pin (bidirectional, programmable) |
| Pin 34 | I/O β User I/O pin (bidirectional, programmable) |
| Pin 35 | I/O β User I/O pin (bidirectional, programmable) |
| Pin 36 | I/O β User I/O pin (bidirectional, programmable) |
| Pin 37 | I/O β User I/O pin (bidirectional, programmable) |
| Pin 38 | I/O β User I/O pin (bidirectional, programmable) |
| Pin 39 | I/O β User I/O pin (bidirectional, programmable) |
| Pin 40 | VCC β +5V supply |
| Pin 41 | I/O β User I/O pin (bidirectional, programmable) |
| Pin 42 | I/O β User I/O pin (bidirectional, programmable) |
| Pin 43 | I/O β User I/O pin (bidirectional, programmable) |
| Pin 44 | I/O β User I/O pin (bidirectional, programmable) |
| Pin 45 | I/O β User I/O pin (bidirectional, programmable) |
| Pin 46 | I/O β User I/O pin (bidirectional, programmable) |
| Pin 47 | I/O β User I/O pin (bidirectional, programmable) |
| Pin 48 | I/O β User I/O pin (bidirectional, programmable) |
| Pin 49 | I/O β User I/O pin (bidirectional, programmable) |
| Pin 50 | GND β Ground |
| Pin 51 | I/O β User I/O pin (bidirectional, programmable) |
| Pin 52 | I/O β User I/O pin (bidirectional, programmable) |
| Pin 53 | I/O β User I/O pin (bidirectional, programmable) |
| Pin 54 | I/O β User I/O pin (bidirectional, programmable) |
| Pin 55 | I/O β User I/O pin (bidirectional, programmable) |
| Pin 56 | I/O β User I/O pin (bidirectional, programmable) |
| Pin 57 | I/O β User I/O pin (bidirectional, programmable) |
| Pin 58 | I/O β User I/O pin (bidirectional, programmable) |
| Pin 59 | I/O β User I/O pin (bidirectional, programmable) |
| Pin 60 | VCC β +5V supply |
| Pin 61 | I/O β User I/O pin (bidirectional, programmable) |
| Pin 62 | I/O β User I/O pin (bidirectional, programmable) |
| Pin 63 | I/O β User I/O pin (bidirectional, programmable) |
| Pin 64 | I/O β User I/O pin (bidirectional, programmable) |
| Pin 65 | I/O β User I/O pin (bidirectional, programmable) |
| Pin 66 | I/O β User I/O pin (bidirectional, programmable) |
| Pin 67 | I/O β User I/O pin (bidirectional, programmable) |
| Pin 68 | I/O β User I/O pin (bidirectional, programmable) |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM5128GI is suitable for 6 applications: Industrial Control Glue Logic, Legacy 5V Bus Address Decoding, Prototype & Engineering Development Platform, Military & Aerospace Reprogrammable Logic, State-Machine Controllers, Legacy Peripheral Interfacing & Glue Logic.
Industrial Control Glue Logic
The EPM5128GI's 128 macrocells and deterministic 55 ns propagation delay make it a strong fit for industrial control glue logic that must run reliably without configuration boot time. Placed between a microcontroller and discrete I/O, it implements custom address decoding, watchdog handshakes, and interrupt prioritization; the ceramic CPGA-68 package provides hermetic sealing for factory-floor environments, while UV-erasability allows firmware revision during controller commissioning without board rework. The 5V supply matches legacy 5V industrial buses (e.g., STD-32, VME), and industrial temperature grade supports -40C to +85C operation typical of plant-floor enclosures.
Recommended
Legacy 5V Bus Address Decoding
The EPM5128GI suits legacy 5V microprocessor bus address decoding where deterministic timing and non-volatile configuration are required. Its 55 ns tPD plus 128 macrocells can decode full 24-bit address spaces with multiple chip-select outputs and registered enables, fitting between a 5V CPU and peripherals like SRAM, ROM, or dual-ported memory. The ceramic CPGA-68 windowed package supports iterative firmware updates during prototype bring-up. Compared to 74LS/74FTTL decoder trees, the EPM5128GI consolidates logic, reduces board area, and offers one-chip revisionability via UV erasure for late-stage address-map changes.
Recommended
Prototype & Engineering Development Platform
The EPM5128GI's UV-transparent ceramic window and 128-cell capacity make it ideal for prototype and pre-production development where logic must be iterated multiple times. Engineers using UV erasers can erase and reprogram the device 100+ times during logic development, with no in-circuit programming infrastructure needed beyond a standard Altera-compatible programmer. The CPGA-68 socketed package allows rapid swap of devices during test campaigns. Industrial temperature grade also lets prototypes move directly into field trials, accelerating time-to-validation for industrial and military designs that will eventually migrate to production OTP or surface-mount variants.
Recommended
Military & Aerospace Reprogrammable Logic
The EPM5128GI's ceramic windowed CPGA-68 package, hermetic sealing, and UV-erasable non-volatile EPROM configuration suit military and aerospace applications where soldered SRAM FPGAs (which lose configuration on power-down) are unacceptable. With industrial temp grade as a baseline and the same Altera die used in military-screened variants, it provides a path for mission-critical avionics, weapons-system interfaces, and satellite command decoders requiring field reprogramming for software updates. The 5V supply rails match legacy MIL-STD-1553 and ARINC-429 interface hardware, and the deterministic 55 ns timing supports strict real-time control loops in flight systems.
Recommended
State-Machine Controllers
The EPM5128GI's deterministic 55 ns timing and abundant macrocell registers make it well-suited for complex state-machine controllers in industrial automation, instrumentation, and embedded control applications. With 128 macrocells providing both combinatorial and registered logic, designers can implement multi-state FSMs, sequencers, and protocol engines without external glue logic. The UV-erasable ceramic package allows FSM revisions during algorithm development, while the non-volatile EPROM storage means the state machine boots instantly on power-up β critical for real-time control where SRAM-based FPGAs introduce unacceptable boot delays. Industrial temperature grade supports factory automation environments.
Recommended
Legacy Peripheral Interfacing & Glue Logic
The EPM5128GI bridges legacy peripherals to modern microprocessors through custom interface glue logic, with 128 macrocells supporting parallel bus arbitration, wait-state generators, and protocol converters. Its 55 ns tPD handles ISA bus and similar 5V interfaces without timing violations, while the CPGA-68 ceramic package survives the thermal cycling of industrial enclosures. UV-erasability lets engineers tweak peripheral timing profiles during validation. The non-volatile configuration eliminates boot-PROM complexity compared to SRAM-based FPGAs, simplifying BOM and improving reliability in long-lifecycle industrial systems that must operate for decades without firmware-service infrastructure.
Recommended
Recommended Products Summary
Engineering reference data for EPM5128GI β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM5128GC | EPM5128GC-1 | EPM5128GC-2 | EPM5128GC2 | EPM5128GI-1 |
|---|---|---|---|---|---|---|
| Brand | Altera | Altera | Altera | Altera | Altera | Altera |
| Package | CPGA-68 (ceramic windowed) | CPGA-68 - same | CPGA-68 - same | CPGA-68 - same | CPGA-68 - same | CPGA-68 - same |
| Macrocells | 128 | 128 | 128 | 128 | 128 | 128 |
| Propagation Delay (tPD) | 55 ns | 55 ns | faster (-1 grade) | faster (-2 grade) | faster (-2 grade) | faster (-1 grade) |
| Supply Voltage | 5 V | 5 V | 5 V | 5 V | 5 V | 5 V |
| Temperature Grade | Industrial | Commercial | Commercial | Commercial | Commercial | Industrial |
| Technology | UV-erasable CMOS EPROM | UV-erasable CMOS EPROM | UV-erasable CMOS EPROM | UV-erasable CMOS EPROM | UV-erasable CMOS EPROM | UV-erasable CMOS EPROM |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
Key Differentiators
- Industrial temperature grade (vs commercial-grade variants) (vs EPM5128GC)
- UV-erasable windowed ceramic package (vs EPM5128GM (military grade))
- Non-volatile EPROM configuration vs SRAM-based FPGAs (vs SRAM-based FPGAs (e.g., Xilinx XC4000 series))
Design Notes
The EPM5128GI uses a CPGA-68 ceramic package that requires a PGA-68 socket β it is NOT surface-mountable. Attempting to hand-solder PGA leads will damage the ceramic body and break the UV-transparent window. Use a machined-pin socket (e.g., 3M Textool or equivalent) for development, and consider socketless PCB designs only for high-reliability production. Always verify the socket's pin numbering matches the Altera datasheet before insertion, as reverse-pin damage will destroy the device.
The EPM5128GI requires a single 5V Β±10% supply with multiple VCC and GND pins distributed around the CPGA-68 package. Decouple each VCC pin with a 0.1 uF ceramic capacitor placed within 5 mm of the pin, plus a bulk 10-47 uF tantalum or aluminum capacitor at the board power entry. The device draws significant inrush current during UV erasure/programming β ensure your supply can deliver the current 200 mA peak with good regulation to prevent programming failures and EPROM read disturb.
Estimated: at 5V supply with all 128 macrocells switching at 18 MHz, the EPM5128GI dissipates approximately 1.5-2.0 W. The CPGA-68 ceramic package has a typical theta_JA of 30-40 C/W without airflow, giving a junction temperature rise of 45-80 C above ambient. For industrial environments with 60 C ambient, ensure adequate airflow or heat-sink attachment to the ceramic lid to keep Tj below 125 C. Always specify industrial-grade (GI) parts, not commercial (GC), for sustained operation above 70 C.
The EPM5128GI's 55 ns tPD is deterministic but I/O pin drive strength is limited (typically 4-8 mA source/sink). For buses with heavy capacitive loading (>50 pF), buffer outputs with external 74LS244/74FCT244 drivers rather than relying on direct CPLD drive. Add 10-33 ohm series damping resistors on high-speed outputs to reduce ground bounce on the CPGA-68 ceramic package, which can exhibit lead inductance around 10 nH per pin at fast edge rates.
Compliance Information
RoHS and REACH status not documented in public Alldatasheet mirror as of 2026-09-12 (marked [DATA_NEEDED] in specs). Ceramic PGA package with through-hole leads predates RoHS enforcement; lead-free and halogen-free status marked unknown β verify with distributor environmental compliance documentation. AEC-Q100 not applicable β this is a programmable logic device, not an automotive-grade IC in the AEC-Q100 sense.
