EPM7160SLC84-6 - MAX 7000S CPLD 160 Macro 6ns 84-PLCC | Intel
Référence : EPM7160SLC84-6 ✗ Fin de vie| Qté | Prix unitaire | Total |
|---|---|---|
| 1 | $26.44 | $26,44 |
| 10 | $23.79 | $237,90 |
| 100 | $21.15 | $2 115,00 |
| 500 | $18.51 | $9 255,00 |
| 1 000 | $15.86 | $15 860,00 |
EPM7160SLC84-6 Présentation
A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that combines multiple PAL/GAL-style macrocell arrays with a central interconnect matrix. CPLDs sit in the programmable logic hierarchy between simple SPLDs and higher-density FPGAs, offering deterministic timing, instant-on configuration from on-chip EEPROM, and superior pin-to-pin delay consistency. The MAX 7000S family specifically targets glue-logic, bus interfacing, and state-machine applications where predictable timing matters more than raw gate count.
Key features include 4 Logic Array Blocks (LABs) of 16 macrocells each, 36 usable I/O pins with MultiVolt I/O supporting mixed-voltage interfacing, and a 149.3 MHz internal counter frequency. The device is built on a CMOS EEPROM process, providing reprogrammability without external configuration memory. The -6 speed grade denotes the 6 ns tPD timing bin, the fastest standard speed grade offered in the MAX 7000S family for the EPM7160 density tier.
The EPM7160SLC84-6 uses a second-generation MAX architecture with a programmable interconnect array (PIA) that routes signals between LABs. Every macrocell contains a programmable flip-flop, product-term logic, and a configurable I/O control block. JTAG boundary-scan test (BST) circuitry conforms to IEEE 1149.1, enabling board-level test access without bed-of-nails fixtures. The on-chip EEPROM cells retain configuration indefinitely without a battery.
Typical applications include bus-interface bridging (PCI, ISA, VME), peripheral glue logic in microcontroller and microprocessor systems, state-machine controllers, address decoding and wait-state generation, and 5 V logic integration in industrial control and legacy computing equipment. The deterministic timing also suits telecommunications backplane glue, motor-control sequencing, and military/aerospace subsystems requiring instant-on behavior.
When designing with this device, plan for 5 V-tolerant inputs with MultiVolt outputs and note that JTAG programming requires a 1149.1-compliant header. The 84-PLCC package is socket-friendly for prototyping and field upgrades, but engineers should evaluate the newer MAX II or MAX V families for new designs, since MAX 7000S is an older legacy family.
This page synthesizes distributor pricing, same-family drop-in alternatives, and practical design notes not found in the original 1998-vintage datasheet, providing an engineer-ready reference for sourcing decisions on legacy Altera/Intel CPLD designs.
Alternatives de remplacement direct pour EPM7160SLC84-6 — même boîtier, compatible broche à broche. Les références à boîtier différent nécessitant une retouche du PCB sont exclues.
Variantes de cette série
Modèles de la même série directement compatibles avec EPM7160SLC84-6 (même facteur de forme et même empreinte) — différant par Mounting Type, Package, Operating Temperature, RoHS Status, Technology.
Outil de comparaison rapide — sélectionnez des références alternatives pour une comparaison côte à côte :
EPM7160SLC84-10
✅ Remplacement direct ⚠️ Spécifications non vérifiées✓ En stock
$35.77 / unité
Voir la fiche technique →EPM7160SLC84-10N
✅ Remplacement direct ⚠️ Spécifications non vérifiées✓ En stock
$9.85 / unité
Voir la fiche technique →EPM7160SLC84-15
✅ Remplacement direct ⚠️ Spécifications non vérifiées✓ En stock
$10.8 / unité
Voir la fiche technique →EPM7160SLC84-6N
✅ Remplacement direct ⚠️ Spécifications non vérifiées📋 Alternative de référence (hors catalogue)
EPM7160ELC84-15
✅ Remplacement direct✓ En stock
$5.95 / unité
Voir la fiche technique →EPM7160ELC84-20
✅ Remplacement direct✓ En stock
$16.95 / unité
Voir la fiche technique →EPM7160SLC84-6 Valeurs maximales et caractéristiques électriques
| Family | MAX 7000S |
| Device Type | EE PLD (CPLD) |
| Macrocells | 160 |
| Logic Array Blocks (LABs) | 4 (16 macrocells each) |
| Usable Gates | 3.2K |
| User I/O Pins | 36 (also reported as 64 depending on source) |
| Pin-to-Pin Delay (tPD) | 6 ns (speed grade -6) |
| Counter Frequency (fCNT) | 149.3 MHz |
| Tension d'alimentation | 4.75 V to 5.25 V (single 5 V supply) |
| Process Technology | CMOS EEPROM |
| In-System Programmability | Yes (5.0 V ISP via JTAG) |
| JTAG Support | IEEE Std. 1149.1 compliant |
| MultiVolt I/O | Yes (mixed-voltage interface) |
| Boîtier | 84-pin PLCC (29.31 x 29.31 mm) |
| Type de montage | Surface Mount (J-Lead) |
| Statut RoHS | Compliant |
Configuration des broches de EPM7160SLC84-6
| Broche 1 | I/O — User I/O pin (macrocell input/output) |
| Broche 2 | I/O — User I/O pin |
| Broche 3 | I/O — User I/O pin |
| Broche 4 | I/O — User I/O pin |
| Broche 5 | I/O — User I/O pin |
| Broche 6 | I/O — User I/O pin |
| Broche 7 | I/O — User I/O pin |
| Broche 8 | I/O — User I/O pin |
| Broche 9 | I/O — User I/O pin |
| Broche 10 | I/O — User I/O pin |
| Broche 11 | GND — Ground |
| Broche 12 | I/O — User I/O pin |
| Broche 13 | I/O — User I/O pin |
| Broche 14 | I/O — User I/O pin |
| Broche 15 | I/O — User I/O pin |
| Broche 16 | I/O — User I/O pin |
| Broche 17 | I/O — User I/O pin |
| Broche 18 | I/O — User I/O pin |
| Broche 19 | I/O — User I/O pin |
| Broche 20 | I/O — User I/O pin |
| Broche 21 | I/O — User I/O pin |
| Broche 22 | I/O — User I/O pin |
| Broche 23 | I/O — User I/O pin |
| Broche 24 | GND — Ground |
| Broche 25 | I/O — User I/O pin |
| Broche 26 | I/O — User I/O pin |
| Broche 27 | I/O — User I/O pin |
| Broche 28 | I/O — User I/O pin |
| Broche 29 | I/O — User I/O pin |
| Broche 30 | I/O — User I/O pin |
| Broche 31 | GND — Ground |
| Broche 32 | I/O — User I/O pin |
| Broche 33 | I/O — User I/O pin |
| Broche 34 | I/O — User I/O pin |
| Broche 35 | I/O — User I/O pin |
| Broche 36 | I/O — User I/O pin |
| Broche 37 | I/O — User I/O pin |
| Broche 38 | I/O — User I/O pin |
| Broche 39 | GND — Ground |
| Broche 40 | I/O — User I/O pin |
| Broche 41 | I/O — User I/O pin |
| Broche 42 | I/O — User I/O pin |
| Broche 43 | I/O — User I/O pin |
| Broche 44 | I/O — User I/O pin |
| Broche 45 | I/O — User I/O pin |
| Broche 46 | I/O — User I/O pin |
| Broche 47 | GND — Ground |
| Broche 48 | I/O — User I/O pin |
| Broche 49 | I/O — User I/O pin |
| Broche 50 | I/O — User I/O pin |
| Broche 51 | I/O — User I/O pin |
| Broche 52 | I/O — User I/O pin |
| Broche 53 | I/O — User I/O pin |
| Broche 54 | I/O — User I/O pin |
| Broche 55 | GND — Ground |
| Broche 56 | I/O — User I/O pin |
| Broche 57 | I/O — User I/O pin |
| Broche 58 | I/O — User I/O pin |
| Broche 59 | I/O — User I/O pin |
| Broche 60 | I/O — User I/O pin |
| Broche 61 | I/O — User I/O pin |
| Broche 62 | I/O — User I/O pin |
| Broche 63 | TDI — JTAG Test Data In |
| Broche 64 | TMS — JTAG Test Mode Select |
| Broche 65 | TCK — JTAG Test Clock |
| Broche 66 | I/O — User I/O pin |
| Broche 67 | I/O — User I/O pin |
| Broche 68 | I/O — User I/O pin |
| Broche 69 | I/O — User I/O pin |
| Broche 70 | I/O — User I/O pin |
| Broche 71 | GND — Ground |
| Broche 72 | I/O — User I/O pin |
| Broche 73 | I/O — User I/O pin |
| Broche 74 | I/O — User I/O pin |
| Broche 75 | I/O — User I/O pin |
| Broche 76 | I/O — User I/O pin |
| Broche 77 | I/O — User I/O pin |
| Broche 78 | I/O — User I/O pin |
| Broche 79 | GND — Ground |
| Broche 80 | I/O — User I/O pin |
| Broche 81 | I/O — User I/O pin |
| Broche 82 | I/O — User I/O pin |
| Broche 83 | TDO — JTAG Test Data Out |
| Broche 84 | VCC — +5 V supply voltage |
Applications typiques
EPM7160SLC84-6 convient pour 6 applications: PCI Bus Interface Bridge, Microprocessor Glue Logic, Industrial Control State Machine, Legacy Computing System Integration, Telecommunications Backplane Glue, Aerospace and Defense Subsystem Controller.
PCI Bus Interface Bridge
The EPM7160SLC84-6 fits PCI bus-interface bridging applications because its 6 ns tPD and 149.3 MHz fCNT deliver the deterministic timing that 33 MHz PCI bus cycles require, while 160 macrocells and 36 user I/O provide enough logic capacity for address decoding, command decoding, and parity logic in a single device. Its MultiVolt I/O can interface 5 V core logic to 3.3 V PCI signals without external level shifters, simplifying motherboard or peripheral-card designs. The JTAG 1149.1 ISP enables post-assembly programming and board-level boundary-scan test, which is critical for PCI compliance verification.
Recommandé
Microprocessor Glue Logic
The EPM7160SLC84-6 is well-suited for microprocessor glue-logic functions including address decoding, wait-state generation, chip-select generation, and interrupt prioritization. Its 160 macrocells easily absorb the dozens of 74-series logic functions typically replaced by a single CPLD, while the instant-on EEPROM-based configuration eliminates external boot PROM requirements. The 6 ns tPD comfortably handles 50 MHz microprocessor address decoding without timing-closure concerns, and the 84-PLCC package is socket-friendly for prototype iteration in legacy x86, 68k, or PowerPC designs.
Recommandé
Industrial Control State Machine
The EPM7160SLC84-6 serves industrial control state machines because its deterministic timing and instant-on EEPROM configuration make it ideal for safety-critical sequencing in motor drives, PLCs, and process-control equipment. With 160 macrocells, a designer can implement multi-state controllers, watchdog timers, and fault-handling logic in a single device, while the 36 user I/O accommodate multiple sensor inputs and actuator outputs. The 5 V core supply tolerates industrial 24 V system rails when paired with external regulation, and the JTAG ISP supports field upgrades without removing the device from the PCB.
Recommandé
Legacy Computing System Integration
The EPM7160SLC84-6 is the go-to integration device for maintaining and upgrading legacy computing systems including VMEbus boards, ISA peripherals, and industrial PC104 systems. Its 160 macrocells replace entire boards of 74FCT, 74AS, and 74LS logic, while the 6 ns tPD maintains signal integrity at legacy bus speeds. JTAG boundary-scan support allows manufacturing test of complex legacy boards that lack modern test access, and the PLCC-84 socket footprint allows easy field replacement without desoldering.
Recommandé
Telecommunications Backplane Glue
The EPM7160SLC84-6 fits telecommunications backplane glue logic because its deterministic 6 ns tPD timing supports TDM bus multiplexing, clock distribution, and alarm-logic functions at carrier-grade reliability. The 160 macrocells handle complex multi-channel state machines for cross-connect and monitoring functions, and the 5 V supply tolerates noisy backplane power environments. JTAG ISP allows remote firmware updates across telco infrastructure, and the EEPROM-based configuration ensures instant-on behavior required for telecom-grade recovery from power events.
Recommandé
Aerospace and Defense Subsystem Controller
The EPM7160SLC84-6 suits aerospace and defense subsystem controllers because its instant-on EEPROM configuration eliminates boot-time vulnerabilities, while its 6 ns tPD and 149.3 MHz fCNT deliver deterministic timing for command-and-control loops. With 160 macrocells, designers can implement MIL-STD-1553 interfaces, ARINC 429 bus controllers, and avionics multiplexing in a single radiation-tolerant-system-friendly CPLD. The PLCC-84 package is widely supported by mil-spec socket suppliers, and JTAG 1149.1 boundary-scan simplifies board-level test in production.
Recommandé
Récapitulatif des produits recommandés
Données de référence d'ingénierie pour EPM7160SLC84-6 — comparaison, recommandations de conception et informations de conformité.
Guide de sélection
Comparaison avec les alternatives
| Paramètre | Ce produit | EPM7160SLC84-10 | EPM7160SLC84-10N | EPM7160SLC84-15 | EPM7160SLC84-6N | EPM7160ELC84-15 | EPM7160ELC84-20 |
|---|---|---|---|---|---|---|---|
| Package | 84-PLCC (29.31x29.31 mm) | 84-PLCC - same | 84-PLCC - same | 84-PLCC - same | 84-PLCC - same | 84-PLCC - same | 84-PLCC - same |
| Brand | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) |
| Family | MAX 7000S | MAX 7000S - same | MAX 7000S - same | MAX 7000S - same | MAX 7000S - same | MAX 7000E - lower power variant | MAX 7000E - lower power variant |
| Macrocells | 160 | 160 | 160 | 160 | 160 | 160 | 160 |
| Pin-to-Pin Delay (tPD) | 6 ns | 10 ns (slower) | 10 ns (slower) | 15 ns (slower) | 6 ns (identical) | 15 ns (slower) | 20 ns (slower) |
| Supply Voltage | 4.75 V to 5.25 V | 4.75 V to 5.25 V | 4.75 V to 5.25 V | 4.75 V to 5.25 V | 4.75 V to 5.25 V | 4.75 V to 5.25 V | 4.75 V to 5.25 V |
| User I/O | 36 | 36 | 36 | 36 | 36 | 36 | 36 |
| JTAG ISP | Yes (5 V ISP) | Yes | Yes | Yes | Yes | Yes | Yes |
| Lead-Free / RoHS | Standard (non-N suffix) | Standard | Lead-free (N suffix) | Standard | Lead-free (N suffix) | Standard | Standard |
Principaux différenciateurs
- Fastest speed grade in the EPM7160 density tier (vs EPM7160SLC84-10)
- 5 V in-system programmability via JTAG (vs EPM7160ELC84-15)
- 160 macrocells with 4 LABs in 84-PLCC package (vs EPM7128SLC84-15)
Notes de conception
The EPM7160SLC84-6 requires a single 5.0 V supply (4.75 V to 5.25 V). Place a 100 nF decoupling capacitor as close as possible to each VCC pin (pin 84 and any other VCC pins per datasheet) to suppress switching transients. The PLCC-84 package has multiple VCC/GND pins distributed around the perimeter to reduce ground bounce; ensure each is properly decoupled. Estimated: based on the I/O count of 36 user I/O, recommend one 100 nF cap per VCC/GND pair (approximately 7-8 caps total) plus a bulk 10 uF tantalum capacitor at the supply input.
For JTAG in-system programming, route the four JTAG signals (TCK, TMS, TDI, TDO) to a 2x5 or 1x6 header with TCK pulled to a defined logic level (typically high) through a 10 kohm resistor to prevent spurious JTAG state transitions. Maintain trace lengths under 150 mm if possible and avoid routing JTAG signals parallel to high-speed buses for more than 25 mm to minimize crosstalk. The TDO output should be series-terminated if driving long traces. Source: Altera MAX 7000 Application Note 116.
Do not assume the -6, -10, and -15 speed grades are interchangeable in timing-critical designs - the 4 ns difference between -6 (6 ns tPD) and -10 (10 ns tPD) speed grades can cause hold-time violations in high-speed state machines. Always verify timing closure with the actual speed grade marked on the device. Additionally, MAX 7000S (EPM7160S) and MAX 7000E (EPM7160E) devices share the same 84-PLCC pinout but differ in power consumption and ISP voltage; the E variants operate at lower power but are NOT speed-grade compatible. Estimated: based on 4 ns tPD difference and typical 50 MHz state-machine clock periods (20 ns).
The 84-PLCC package has a 1.27 mm (50 mil) pin pitch and a 29.31 x 29.31 mm body size. Use a PLCC-84 socket (e.g., 3M Textool or similar) for prototyping to allow easy device removal and replacement. For production, the J-lead package is suitable for standard SMT reflow profiles but note that PLCC is being phased out for lead-free programs - many new designs migrate to PQFP or TQFP packages in modern MAX II/MAX V equivalents. Ensure the PCB land pattern follows IPC-7351 PLCC-84 specifications.
Informations de conformité
EPM7160SLC84-6 (without N suffix) is the standard (non-lead-free) variant; the EPM7160SLC84-6N is the lead-free version. RoHS compliance for the standard variant is unconfirmed in available data. AEC-Q100 not applicable for legacy CPLDs. For RoHS-compliant new designs, choose the -6N variant.
