EPM7160SLC84-6 - MAX 7000S CPLD 160 Macro 6ns 84-PLCC | Intel
MPN: EPM7160SLC84-6 β End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $26.44 | $26.44 |
| 10 | $23.79 | $237.90 |
| 100 | $21.15 | $2,115.00 |
| 500 | $18.51 | $9,255.00 |
| 1,000 | $15.86 | $15,860.00 |
Drop-in alternatives for EPM7160SLC84-6 β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
EPM7160SLC84-10
β Drop-In β οΈ εζ°εΎ ιͺθ―β In Stock
$35.77 / Unit
View Datasheet βEPM7160SLC84-10N
β Drop-In β οΈ εζ°εΎ ιͺθ―β In Stock
$9.85 / Unit
View Datasheet βEPM7160SLC84-15
β Drop-In β οΈ εζ°εΎ ιͺθ―β In Stock
$10.8 / Unit
View Datasheet βEPM7160SLC84-6N
β Drop-In β οΈ εζ°εΎ ιͺθ―π Reference alternative (not in catalog)
EPM7160ELC84-15
β Drop-Inβ In Stock
$5.95 / Unit
View Datasheet βEPM7160ELC84-20
β Drop-Inβ In Stock
$16.95 / Unit
View Datasheet βEPM7160SLC84-6 Maximum Ratings & Electrical Characteristics
| Family | MAX 7000S |
| Device Type | EE PLD (CPLD) |
| Macrocells | 160 |
| Logic Array Blocks (LABs) | 4 (16 macrocells each) |
| Usable Gates | 3.2K |
| User I/O Pins | 36 (also reported as 64 depending on source) |
| Pin-to-Pin Delay (tPD) | 6 ns (speed grade -6) |
| Counter Frequency (fCNT) | 149.3 MHz |
| Supply Voltage | 4.75 V to 5.25 V (single 5 V supply) |
| Process Technology | CMOS EEPROM |
| In-System Programmability | Yes (5.0 V ISP via JTAG) |
| JTAG Support | IEEE Std. 1149.1 compliant |
| MultiVolt I/O | Yes (mixed-voltage interface) |
| Package | 84-pin PLCC (29.31 x 29.31 mm) |
| Mounting Type | Surface Mount (J-Lead) |
| RoHS Status | Compliant |
EPM7160SLC84-6 Pin Configuration
| Pin 1 | I/O β User I/O pin (macrocell input/output) |
| Pin 2 | I/O β User I/O pin |
| Pin 3 | I/O β User I/O pin |
| Pin 4 | I/O β User I/O pin |
| Pin 5 | I/O β User I/O pin |
| Pin 6 | I/O β User I/O pin |
| Pin 7 | I/O β User I/O pin |
| Pin 8 | I/O β User I/O pin |
| Pin 9 | I/O β User I/O pin |
| Pin 10 | I/O β User I/O pin |
| Pin 11 | GND β Ground |
| Pin 12 | I/O β User I/O pin |
| Pin 13 | I/O β User I/O pin |
| Pin 14 | I/O β User I/O pin |
| Pin 15 | I/O β User I/O pin |
| Pin 16 | I/O β User I/O pin |
| Pin 17 | I/O β User I/O pin |
| Pin 18 | I/O β User I/O pin |
| Pin 19 | I/O β User I/O pin |
| Pin 20 | I/O β User I/O pin |
| Pin 21 | I/O β User I/O pin |
| Pin 22 | I/O β User I/O pin |
| Pin 23 | I/O β User I/O pin |
| Pin 24 | GND β Ground |
| Pin 25 | I/O β User I/O pin |
| Pin 26 | I/O β User I/O pin |
| Pin 27 | I/O β User I/O pin |
| Pin 28 | I/O β User I/O pin |
| Pin 29 | I/O β User I/O pin |
| Pin 30 | I/O β User I/O pin |
| Pin 31 | GND β Ground |
| Pin 32 | I/O β User I/O pin |
| Pin 33 | I/O β User I/O pin |
| Pin 34 | I/O β User I/O pin |
| Pin 35 | I/O β User I/O pin |
| Pin 36 | I/O β User I/O pin |
| Pin 37 | I/O β User I/O pin |
| Pin 38 | I/O β User I/O pin |
| Pin 39 | GND β Ground |
| Pin 40 | I/O β User I/O pin |
| Pin 41 | I/O β User I/O pin |
| Pin 42 | I/O β User I/O pin |
| Pin 43 | I/O β User I/O pin |
| Pin 44 | I/O β User I/O pin |
| Pin 45 | I/O β User I/O pin |
| Pin 46 | I/O β User I/O pin |
| Pin 47 | GND β Ground |
| Pin 48 | I/O β User I/O pin |
| Pin 49 | I/O β User I/O pin |
| Pin 50 | I/O β User I/O pin |
| Pin 51 | I/O β User I/O pin |
| Pin 52 | I/O β User I/O pin |
| Pin 53 | I/O β User I/O pin |
| Pin 54 | I/O β User I/O pin |
| Pin 55 | GND β Ground |
| Pin 56 | I/O β User I/O pin |
| Pin 57 | I/O β User I/O pin |
| Pin 58 | I/O β User I/O pin |
| Pin 59 | I/O β User I/O pin |
| Pin 60 | I/O β User I/O pin |
| Pin 61 | I/O β User I/O pin |
| Pin 62 | I/O β User I/O pin |
| Pin 63 | TDI β JTAG Test Data In |
| Pin 64 | TMS β JTAG Test Mode Select |
| Pin 65 | TCK β JTAG Test Clock |
| Pin 66 | I/O β User I/O pin |
| Pin 67 | I/O β User I/O pin |
| Pin 68 | I/O β User I/O pin |
| Pin 69 | I/O β User I/O pin |
| Pin 70 | I/O β User I/O pin |
| Pin 71 | GND β Ground |
| Pin 72 | I/O β User I/O pin |
| Pin 73 | I/O β User I/O pin |
| Pin 74 | I/O β User I/O pin |
| Pin 75 | I/O β User I/O pin |
| Pin 76 | I/O β User I/O pin |
| Pin 77 | I/O β User I/O pin |
| Pin 78 | I/O β User I/O pin |
| Pin 79 | GND β Ground |
| Pin 80 | I/O β User I/O pin |
| Pin 81 | I/O β User I/O pin |
| Pin 82 | I/O β User I/O pin |
| Pin 83 | TDO β JTAG Test Data Out |
| Pin 84 | VCC β +5 V supply voltage |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM7160SLC84-6 is suitable for 6 applications: PCI Bus Interface Bridge, Microprocessor Glue Logic, Industrial Control State Machine, Legacy Computing System Integration, Telecommunications Backplane Glue, Aerospace and Defense Subsystem Controller.
PCI Bus Interface Bridge
The EPM7160SLC84-6 fits PCI bus-interface bridging applications because its 6 ns tPD and 149.3 MHz fCNT deliver the deterministic timing that 33 MHz PCI bus cycles require, while 160 macrocells and 36 user I/O provide enough logic capacity for address decoding, command decoding, and parity logic in a single device. Its MultiVolt I/O can interface 5 V core logic to 3.3 V PCI signals without external level shifters, simplifying motherboard or peripheral-card designs. The JTAG 1149.1 ISP enables post-assembly programming and board-level boundary-scan test, which is critical for PCI compliance verification.
Recommended
Microprocessor Glue Logic
The EPM7160SLC84-6 is well-suited for microprocessor glue-logic functions including address decoding, wait-state generation, chip-select generation, and interrupt prioritization. Its 160 macrocells easily absorb the dozens of 74-series logic functions typically replaced by a single CPLD, while the instant-on EEPROM-based configuration eliminates external boot PROM requirements. The 6 ns tPD comfortably handles 50 MHz microprocessor address decoding without timing-closure concerns, and the 84-PLCC package is socket-friendly for prototype iteration in legacy x86, 68k, or PowerPC designs.
Recommended
Industrial Control State Machine
The EPM7160SLC84-6 serves industrial control state machines because its deterministic timing and instant-on EEPROM configuration make it ideal for safety-critical sequencing in motor drives, PLCs, and process-control equipment. With 160 macrocells, a designer can implement multi-state controllers, watchdog timers, and fault-handling logic in a single device, while the 36 user I/O accommodate multiple sensor inputs and actuator outputs. The 5 V core supply tolerates industrial 24 V system rails when paired with external regulation, and the JTAG ISP supports field upgrades without removing the device from the PCB.
Recommended
Legacy Computing System Integration
The EPM7160SLC84-6 is the go-to integration device for maintaining and upgrading legacy computing systems including VMEbus boards, ISA peripherals, and industrial PC104 systems. Its 160 macrocells replace entire boards of 74FCT, 74AS, and 74LS logic, while the 6 ns tPD maintains signal integrity at legacy bus speeds. JTAG boundary-scan support allows manufacturing test of complex legacy boards that lack modern test access, and the PLCC-84 socket footprint allows easy field replacement without desoldering.
Recommended
Telecommunications Backplane Glue
The EPM7160SLC84-6 fits telecommunications backplane glue logic because its deterministic 6 ns tPD timing supports TDM bus multiplexing, clock distribution, and alarm-logic functions at carrier-grade reliability. The 160 macrocells handle complex multi-channel state machines for cross-connect and monitoring functions, and the 5 V supply tolerates noisy backplane power environments. JTAG ISP allows remote firmware updates across telco infrastructure, and the EEPROM-based configuration ensures instant-on behavior required for telecom-grade recovery from power events.
Recommended
Aerospace and Defense Subsystem Controller
The EPM7160SLC84-6 suits aerospace and defense subsystem controllers because its instant-on EEPROM configuration eliminates boot-time vulnerabilities, while its 6 ns tPD and 149.3 MHz fCNT deliver deterministic timing for command-and-control loops. With 160 macrocells, designers can implement MIL-STD-1553 interfaces, ARINC 429 bus controllers, and avionics multiplexing in a single radiation-tolerant-system-friendly CPLD. The PLCC-84 package is widely supported by mil-spec socket suppliers, and JTAG 1149.1 boundary-scan simplifies board-level test in production.
Recommended
Recommended Products Summary
Engineering reference data for EPM7160SLC84-6 β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM7160SLC84-10 | EPM7160SLC84-10N | EPM7160SLC84-15 | EPM7160SLC84-6N | EPM7160ELC84-15 | EPM7160ELC84-20 |
|---|---|---|---|---|---|---|---|
| Package | 84-PLCC (29.31x29.31 mm) | 84-PLCC - same | 84-PLCC - same | 84-PLCC - same | 84-PLCC - same | 84-PLCC - same | 84-PLCC - same |
| Brand | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) |
| Family | MAX 7000S | MAX 7000S - same | MAX 7000S - same | MAX 7000S - same | MAX 7000S - same | MAX 7000E - lower power variant | MAX 7000E - lower power variant |
| Macrocells | 160 | 160 | 160 | 160 | 160 | 160 | 160 |
| Pin-to-Pin Delay (tPD) | 6 ns | 10 ns (slower) | 10 ns (slower) | 15 ns (slower) | 6 ns (identical) | 15 ns (slower) | 20 ns (slower) |
| Counter Frequency (fCNT) | 149.3 MHz | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] | 149.3 MHz (identical) | [DATA_NEEDED] | [DATA_NEEDED] |
| Supply Voltage | 4.75 V to 5.25 V | 4.75 V to 5.25 V | 4.75 V to 5.25 V | 4.75 V to 5.25 V | 4.75 V to 5.25 V | 4.75 V to 5.25 V | 4.75 V to 5.25 V |
| User I/O | 36 | 36 | 36 | 36 | 36 | 36 | 36 |
| JTAG ISP | Yes (5 V ISP) | Yes | Yes | Yes | Yes | Yes | Yes |
| Lead-Free / RoHS | Standard (non-N suffix) | Standard | Lead-free (N suffix) | Standard | Lead-free (N suffix) | Standard | Standard |
Key Differentiators
- Fastest speed grade in the EPM7160 density tier (vs EPM7160SLC84-10)
- 5 V in-system programmability via JTAG (vs EPM7160ELC84-15)
- 160 macrocells with 4 LABs in 84-PLCC package (vs EPM7128SLC84-15)
Design Notes
The EPM7160SLC84-6 requires a single 5.0 V supply (4.75 V to 5.25 V). Place a 100 nF decoupling capacitor as close as possible to each VCC pin (pin 84 and any other VCC pins per datasheet) to suppress switching transients. The PLCC-84 package has multiple VCC/GND pins distributed around the perimeter to reduce ground bounce; ensure each is properly decoupled. Estimated: based on the I/O count of 36 user I/O, recommend one 100 nF cap per VCC/GND pair (approximately 7-8 caps total) plus a bulk 10 uF tantalum capacitor at the supply input.
For JTAG in-system programming, route the four JTAG signals (TCK, TMS, TDI, TDO) to a 2x5 or 1x6 header with TCK pulled to a defined logic level (typically high) through a 10 kohm resistor to prevent spurious JTAG state transitions. Maintain trace lengths under 150 mm if possible and avoid routing JTAG signals parallel to high-speed buses for more than 25 mm to minimize crosstalk. The TDO output should be series-terminated if driving long traces. Source: Altera MAX 7000 Application Note 116.
Do not assume the -6, -10, and -15 speed grades are interchangeable in timing-critical designs - the 4 ns difference between -6 (6 ns tPD) and -10 (10 ns tPD) speed grades can cause hold-time violations in high-speed state machines. Always verify timing closure with the actual speed grade marked on the device. Additionally, MAX 7000S (EPM7160S) and MAX 7000E (EPM7160E) devices share the same 84-PLCC pinout but differ in power consumption and ISP voltage; the E variants operate at lower power but are NOT speed-grade compatible. Estimated: based on 4 ns tPD difference and typical 50 MHz state-machine clock periods (20 ns).
The 84-PLCC package has a 1.27 mm (50 mil) pin pitch and a 29.31 x 29.31 mm body size. Use a PLCC-84 socket (e.g., 3M Textool or similar) for prototyping to allow easy device removal and replacement. For production, the J-lead package is suitable for standard SMT reflow profiles but note that PLCC is being phased out for lead-free programs - many new designs migrate to PQFP or TQFP packages in modern MAX II/MAX V equivalents. Ensure the PCB land pattern follows IPC-7351 PLCC-84 specifications.
Compliance Information
EPM7160SLC84-6 (without N suffix) is the standard (non-lead-free) variant; the EPM7160SLC84-6N is the lead-free version. RoHS compliance for the standard variant is unconfirmed in available data. AEC-Q100 not applicable for legacy CPLDs. For RoHS-compliant new designs, choose the -6N variant.
