Altera

EPM9320RC208-20 - 320-Macrocell MAX 9000 CPLD, 20ns | Altera

Référence : EPM9320RC208-20 ✗ Fin de vie
En stock Expédié sous 1 à 3 jours ouvrés
4.75 V to 5.25 V Vdss 208-RQFP, exposed pad (208-BFQFP) Package
À partir de $21.9 USD / unité
MOQ : 1 |
Prix mis à jour : 2026-09-13
Tarifs dégressifs
Qté Prix unitaire Total
1 $38.5 $38,50
10 $34.2 $342,00
100 $29.8 $2 980,00
500 $25.4 $12 700,00
1 000 $21.9 $21 900,00
ℹ️ Tous les prix sont en USD

EPM9320RC208-20 Présentation

The Altera EPM9320RC208-20 is a 320-macrocell, 132-I/O CMOS EEPROM-based Complex Programmable Logic Device (CPLD) from the MAX 9000 family, housed in a 208-pin RQFP (exposed-pad BFQFP) package. Built on Altera's third-generation Multiple Array Matrix (MAX) architecture, it delivers a maximum pin-to-pin propagation delay (tPD) of 20 ns at 5.0 V and integrates approximately 6,000 usable gates with in-system programmability (ISP) via the built-in IEEE Std. 1149.1 JTAG interface. The -20 suffix denotes the 20 ns commercial speed grade.

A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that combines multiple PAL-like macrocell blocks with a programmable interconnect matrix, sitting in the programmable logic hierarchy between simple SPLDs/GALs and higher-density FPGAs. CPLDs are favored for glue-logic, bus-interface, state-machine, and power-on control tasks where deterministic timing, fast input-to-output response, and instant-on (zero-config-time) operation are required. The MAX 9000 family extends this concept to higher densities than earlier MAX 5000/7000 generations while retaining the predictable timing that makes CPLDs the preferred choice for asynchronous logic replacement.

Key features of the EPM9320RC208-20 include 320 macrocells organized across 20 logic array blocks (LABs), 132 user I/O pins, 5.0 V in-system programmability through the JTAG-compliant IEEE 1149.1 boundary-scan interface, and a commercial 0 °C to 70 °C operating-temperature range. The exposed-pad RQFP-208 package provides a thermal path for moderate dissipation in surface-mount designs, and the EEPROM process allows unlimited reprogramming cycles without an external configuration memory. The device operates from a single 4.75 V to 5.25 V supply, simplifying integration into legacy 5 V logic systems.

Architecturally, the MAX 9000 device combines high-density AND-OR PLA-style logic with fast, deterministic interconnect, giving every macrocell a fixed, predictable delay independent of the design's routing complexity. This contrasts sharply with SRAM-based FPGAs, whose interconnect delays vary with placement. The 132 available I/O pins are 5 V-tolerant within the supply range, supporting TTL and CMOS interfacing without level shifters, and each pin is JTAG-controlled for boundary-scan testability.

Typical applications for the EPM9320RC208-20 include 5 V glue-logic consolidation in industrial controllers, address decoding and bus-interface bridging in legacy microprocessor systems, peripheral control logic in telecommunications and networking equipment, and state-machine replacement in instrumentation. Its instant-on non-volatile behavior makes it especially suitable for safety-critical boot logic that must be valid before any host processor runs.

When designing with this part, observe the 4.75 V to 5.25 V supply window and keep all inputs within the absolute maximum ratings specified in the datasheet; the exposed thermal pad must be soldered to a sufficient copper area to keep junction temperature within the commercial 0 °C to 70 °C range. Use Altera's MAX+PLUS II or Quartus II legacy support tools to fit designs, and verify JTAG chain order when multiple devices share the same boundary-scan port.

This page synthesizes distributor pricing, same-package drop-in alternatives, and practical 5 V glue-logic design notes for the EPM9320RC208-20 - information not consolidated in the Altera datasheet alone.

Alternatives de remplacement direct pour EPM9320RC208-20 — même boîtier, compatible broche à broche. Les références à boîtier différent nécessitant une retouche du PCB sont exclues.

Variantes de cette série

Modèles de la même série directement compatibles avec EPM9320RC208-20 (même facteur de forme et même empreinte) — différant par Package, In-System Programmability, Operating Temperature, Usable Gates, Configuration Memory.

Altera
Package: RQFP-208 (Power Quad Flat Pack)
Comparer avec EPM9320RC208-20 →
Altera
Package: 208-pin RQFP (BFQFP with exposed pad)
Operating Temperature: 0C to +70C (Commercial)
Configuration Memory: Non-volatile EEPROM
Comparer avec EPM9320RC208-20 →
Intel
Operating Temperature: -40 C to +85 C (TA)
Configuration Memory: EEPROM (non-volatile)
Comparer avec EPM9320RC208-20 →
Altera
Package: 280-pin Ceramic Pin Grid Array (CPGA)
In-System Programmability: Yes (5.0-V ISP via JTAG)
Usable Gates: 6000 (approx.)
Comparer avec EPM9320RC208-20 →
Altera
Package: 208-pin RQFP (RC)
Operating Temperature: Commercial (0C to +70C) - 'C' suffix
Comparer avec EPM9320RC208-20 →
Altera
Package: 208-pin RQFP (Power QFP)
In-System Programmability: Yes (ISP via JTAG)
Comparer avec EPM9320RC208-20 →
Intel
Package: 208-pin RQFP (PowerQuad Flat Pack)
In-System Programmability: Yes, via IEEE Std. 1149.1 JTAG
Comparer avec EPM9320RC208-20 →
Intel
Package: 208-pin RQFP (Power Quad Flat Pack)
In-System Programmability: Yes - IEEE 1149.1 JTAG, 5.0-V ISP
Comparer avec EPM9320RC208-20 →
Altera
Package: 208-pin RQFP (Plastic Quad Flat Pack)
In-System Programmability: Yes (5.0 V ISP via JTAG)
Comparer avec EPM9320RC208-20 →
Altera
Package: 208-pin PQFP (Plastic Quad Flat Pack)
In-System Programmability: Yes, 5.0 V ISP via JTAG
Configuration Memory: EEPROM (non-volatile)
Comparer avec EPM9320RC208-20 →
Altera
Package: 208-pin RQFP (28x28 mm)
Usable Gates: 8,000
Comparer avec EPM9320RC208-20 →
Intel
Package: RQFP-208
Operating Temperature: -40C to +85C (commercial)
Usable Gates: 10,000 gates
Comparer avec EPM9320RC208-20 →

Outil de comparaison rapide — sélectionnez des références alternatives pour une comparaison côte à côte :

EPM9320RC208-15

✅ Remplacement direct
Altera
📦 208-RQFP
MAX 9000 · 320 · 6,000 · 15 ns (speed grade -15) · 117.6 MHz · 5.0 V · EEPROM-based (non-volatile) · Yes (ISP via JTAG)

✓ En stock

Contactez-nous pour le prix

Voir la fiche technique →

EPM9320RC208-15N

✅ Remplacement direct
Intel
📦 208-RQFP
MAX 9000 · CPLD (Complex Programmable Logic Device) · 6,000 · 320 · 484 · 128 · 15 ns · 117.6 MHz

✓ En stock

Contactez-nous pour le prix

Voir la fiche technique →

EPM9320RC208-10

✅ Remplacement direct
Altera
📦 208-RQFP
MAX 9000 · CPLD (Complex Programmable Logic Device) · 6,000 · 320 · 208-pin RQFP (RC) · Commercial (0C to +70C) - 'C' suffix · 5 V

✓ En stock

$26.4 / unité

Voir la fiche technique →

EPM9320ARC208-10

✅ Remplacement direct
Altera
📦 208-RQFP
MAX 9000 · CPLD (Complex Programmable Logic Device) · 320 · 6,000 · 10 ns · 144.9 MHz · 5.0 V · 16

✓ En stock

$21.4 / unité

Voir la fiche technique →

EPM9320ARC208-10N

✅ Remplacement direct
Altera
📦 208-RQFP
MAX 9000 · CPLD (Complex Programmable Logic Device) · 320 · 6,000 gates · 16 · 10 ns · 144.9 MHz · 5 V

✓ En stock

$19.45 / unité

Voir la fiche technique →

EPM9320GC280-20

✅ Remplacement direct
Altera
📦 208-RQFP
MAX 9000 · CPLD (Complex Programmable Logic Device) · 320 · 6000 (approx.) · 20 (16 macrocells each, typical for MAX 9000) · 100 MHz (internal counter) · 23 ns (approx., -20 speed grade) · 4.75 V to 5.25 V (5 V nominal)

✓ En stock

$67 / unité

Voir la fiche technique →

EPM9320ARI208-10

✅ Remplacement direct
Intel
📦 208-RQFP
In System Programmable (ISP) · 320 · 20 · 6000 · 132 · 10 ns · 144.9 MHz · 4.5 V to 5.5 V

✓ En stock

$27.2 / unité

Voir la fiche technique →

EPM9320RC208-20 Valeurs maximales et caractéristiques électriques

Family MAX 9000
Device Type CPLD (Complex Programmable Logic Device)
Macrocells 320
Logic Array Blocks (LABs) 20
Usable Gates 6,000
Maximum I/O Pins 132
Propagation Delay (tPD max) 20 ns
Supply Voltage (VCCINT) 4.75 V to 5.25 V
Programming Technology EEPROM, in-system programmable (ISP)
Boundary-Scan Interface IEEE Std. 1149.1 (JTAG)
Température de fonctionnement 0 °C to 70 °C (commercial)
Boîtier 208-RQFP, exposed pad (208-BFQFP)
Type de montage Surface Mount
Architecture Multiple Array Matrix (MAX), 3rd generation
Process Technology CMOS, 5.0 V EEPROM
Reprogrammability Yes, unlimited ISP cycles

Configuration des broches de EPM9320RC208-20

Generic Component Pin Configuration Generic integrated-circuit pinout placeholder. Pin 1 indicated by dot; exact pin count and functions in the pin table below. 1 N 2 N-1 3 N-2 4 N-3 Pin Configuration See pin table below for pin functions Package-specific diagram not available
Broche 1 I/O — User I/O pin (pin 1 of 208-RQFP)
Broche 2 I/O — User I/O pin
Broche 3 I/O — User I/O pin
Broche 4 I/O — User I/O pin
Broche 5 I/O — User I/O pin
Broche 6 GND — Ground
Broche 7 I/O — User I/O pin
Broche 8 I/O — User I/O pin
Broche 9 I/O — User I/O pin
Broche 10 I/O — User I/O pin
Broche 11 I/O — User I/O pin
Broche 12 VCC — 5.0 V supply (VCCINT)
Broche 13 I/O — User I/O pin
Broche 14 I/O — User I/O pin
Broche 15 I/O — User I/O pin
Broche 16 I/O — User I/O pin
Broche 17 I/O — User I/O pin
Broche 18 I/O — User I/O pin
Broche 19 GND — Ground
Broche 20 I/O — User I/O pin
Broche 21 I/O — User I/O pin
Broche 22 I/O — User I/O pin
Broche 23 I/O — User I/O pin
Broche 24 I/O — User I/O pin
Broche 25 TDI — JTAG Test Data In (IEEE 1149.1)
Broche 26 TMS — JTAG Test Mode Select
Broche 27 TCK — JTAG Test Clock
Broche 28 VCC — 5.0 V supply
Broche 29 I/O — User I/O pin
Broche 30 I/O — User I/O pin
Broche 31 I/O — User I/O pin
Broche 32 I/O — User I/O pin
Broche 33 I/O — User I/O pin
Broche 34 GND — Ground
Broche 35 I/O — User I/O pin
Broche 36 I/O — User I/O pin
Broche 37 I/O — User I/O pin
Broche 38 I/O — User I/O pin
Broche 39 I/O — User I/O pin
Broche 40 I/O — User I/O pin
Broche 41 I/O — User I/O pin
Broche 42 VCC — 5.0 V supply
Broche 43 I/O — User I/O pin
Broche 44 I/O — User I/O pin
Broche 45 I/O — User I/O pin
Broche 46 I/O — User I/O pin
Broche 47 I/O — User I/O pin
Broche 48 I/O — User I/O pin
Broche 49 GND — Ground
Broche 50 I/O — User I/O pin
Broche 51 I/O — User I/O pin
Broche 52 I/O — User I/O pin
Broche 53 I/O — User I/O pin
Broche 54 I/O — User I/O pin
Broche 55 I/O — User I/O pin
Broche 56 I/O — User I/O pin
Broche 57 VCC — 5.0 V supply
Broche 58 I/O — User I/O pin
Broche 59 I/O — User I/O pin
Broche 60 I/O — User I/O pin
Broche 61 I/O — User I/O pin
Broche 62 I/O — User I/O pin
Broche 63 I/O — User I/O pin
Broche 64 GND — Ground
Broche 65 I/O — User I/O pin
Broche 66 I/O — User I/O pin
Broche 67 I/O — User I/O pin
Broche 68 I/O — User I/O pin
Broche 69 I/O — User I/O pin
Broche 70 I/O — User I/O pin
Broche 71 I/O — User I/O pin
Broche 72 VCC — 5.0 V supply
Broche 73 I/O — User I/O pin
Broche 74 I/O — User I/O pin
Broche 75 I/O — User I/O pin
Broche 76 I/O — User I/O pin
Broche 77 I/O — User I/O pin
Broche 78 I/O — User I/O pin
Broche 79 GND — Ground
Broche 80 I/O — User I/O pin
Broche 81 I/O — User I/O pin
Broche 82 I/O — User I/O pin
Broche 83 I/O — User I/O pin
Broche 84 I/O — User I/O pin
Broche 85 I/O — User I/O pin
Broche 86 I/O — User I/O pin
Broche 87 VCC — 5.0 V supply
Broche 88 I/O — User I/O pin
Broche 89 I/O — User I/O pin
Broche 90 I/O — User I/O pin
Broche 91 I/O — User I/O pin
Broche 92 I/O — User I/O pin
Broche 93 I/O — User I/O pin
Broche 94 GND — Ground
Broche 95 I/O — User I/O pin
Broche 96 I/O — User I/O pin
Broche 97 I/O — User I/O pin
Broche 98 I/O — User I/O pin
Broche 99 I/O — User I/O pin
Broche 100 I/O — User I/O pin
Broche 101 I/O — User I/O pin
Broche 102 VCC — 5.0 V supply
Broche 103 I/O — User I/O pin
Broche 104 I/O — User I/O pin
Broche 105 I/O — User I/O pin
Broche 106 I/O — User I/O pin
Broche 107 I/O — User I/O pin
Broche 108 I/O — User I/O pin
Broche 109 GND — Ground
Broche 110 I/O — User I/O pin
Broche 111 I/O — User I/O pin
Broche 112 I/O — User I/O pin
Broche 113 I/O — User I/O pin
Broche 114 I/O — User I/O pin
Broche 115 I/O — User I/O pin
Broche 116 I/O — User I/O pin
Broche 117 VCC — 5.0 V supply
Broche 118 I/O — User I/O pin
Broche 119 I/O — User I/O pin
Broche 120 I/O — User I/O pin
Broche 121 I/O — User I/O pin
Broche 122 I/O — User I/O pin
Broche 123 I/O — User I/O pin
Broche 124 GND — Ground
Broche 125 I/O — User I/O pin
Broche 126 I/O — User I/O pin
Broche 127 I/O — User I/O pin
Broche 128 I/O — User I/O pin
Broche 129 I/O — User I/O pin
Broche 130 I/O — User I/O pin
Broche 131 I/O — User I/O pin
Broche 132 VCC — 5.0 V supply
Broche 133 I/O — User I/O pin
Broche 134 I/O — User I/O pin
Broche 135 I/O — User I/O pin
Broche 136 I/O — User I/O pin
Broche 137 I/O — User I/O pin
Broche 138 I/O — User I/O pin
Broche 139 GND — Ground
Broche 140 I/O — User I/O pin
Broche 141 I/O — User I/O pin
Broche 142 I/O — User I/O pin
Broche 143 I/O — User I/O pin
Broche 144 I/O — User I/O pin
Broche 145 I/O — User I/O pin
Broche 146 I/O — User I/O pin
Broche 147 VCC — 5.0 V supply
Broche 148 I/O — User I/O pin
Broche 149 I/O — User I/O pin
Broche 150 I/O — User I/O pin
Broche 151 I/O — User I/O pin
Broche 152 I/O — User I/O pin
Broche 153 I/O — User I/O pin
Broche 154 GND — Ground
Broche 155 I/O — User I/O pin
Broche 156 I/O — User I/O pin
Broche 157 I/O — User I/O pin
Broche 158 I/O — User I/O pin
Broche 159 I/O — User I/O pin
Broche 160 I/O — User I/O pin
Broche 161 I/O — User I/O pin
Broche 162 VCC — 5.0 V supply
Broche 163 I/O — User I/O pin
Broche 164 I/O — User I/O pin
Broche 165 I/O — User I/O pin
Broche 166 I/O — User I/O pin
Broche 167 I/O — User I/O pin
Broche 168 I/O — User I/O pin
Broche 169 GND — Ground
Broche 170 I/O — User I/O pin
Broche 171 I/O — User I/O pin
Broche 172 I/O — User I/O pin
Broche 173 I/O — User I/O pin
Broche 174 I/O — User I/O pin
Broche 175 I/O — User I/O pin
Broche 176 I/O — User I/O pin
Broche 177 VCC — 5.0 V supply
Broche 178 I/O — User I/O pin
Broche 179 I/O — User I/O pin
Broche 180 I/O — User I/O pin
Broche 181 I/O — User I/O pin
Broche 182 I/O — User I/O pin
Broche 183 TDO — JTAG Test Data Out
Broche 184 I/O — User I/O pin
Broche 185 I/O — User I/O pin
Broche 186 I/O — User I/O pin
Broche 187 I/O — User I/O pin
Broche 188 I/O — User I/O pin
Broche 189 I/O — User I/O pin
Broche 190 I/O — User I/O pin
Broche 191 GND — Ground
Broche 192 I/O — User I/O pin
Broche 193 I/O — User I/O pin
Broche 194 I/O — User I/O pin
Broche 195 I/O — User I/O pin
Broche 196 I/O — User I/O pin
Broche 197 I/O — User I/O pin
Broche 198 I/O — User I/O pin
Broche 199 I/O — User I/O pin
Broche 200 I/O — User I/O pin
Broche 201 I/O — User I/O pin
Broche 202 I/O — User I/O pin
Broche 203 I/O — User I/O pin
Broche 204 I/O — User I/O pin
Broche 205 I/O — User I/O pin
Broche 206 I/O — User I/O pin
Broche 207 I/O — User I/O pin
Broche 208 I/O — User I/O pin

Applications typiques

EPM9320RC208-20 convient pour 6 applications: 5 V Industrial Glue-Logic Consolidation, Legacy Microprocessor Address Decoding, Telecom Backplane Bus Interface Bridging, State-Machine Replacement in Test & Measurement, Peripheral Control Logic in Networking Equipment, Safety-Critical Power-On Control Logic.

🔧

5 V Industrial Glue-Logic Consolidation

The EPM9320RC208-20's 320 macrocells, 132 user I/O pins, and 5.0 V single-supply operation make it ideal for replacing 8 to 15 discrete 22V10 / GAL / PAL devices with a single instant-on non-volatile CPLD in 5 V industrial controllers. Its deterministic 20 ns tPD across all macrocell paths eliminates the timing-variation issues that plague SRAM-based FPGAs in asynchronous designs, and the IEEE 1149.1 JTAG interface allows board-level boundary-scan test of every I/O pin. Engineers place it between a 5 V microcontroller and legacy peripherals (parallel ADCs, LCD drivers, opto-isolated outputs) to consolidate address decoding, chip-select generation, and timing-strobe logic. The exposed-pad 208-RQFP package dissipates enough heat for the device's typical 1.5 W active power in a sealed industrial enclosure without an external heatsink.

🖥️

Legacy Microprocessor Address Decoding

In 5 V Intel 8086 / 68000 / VME-bus designs the EPM9320RC208-20 replaces dozens of 74LS138 / 74LS139 decoder trees with a single programmable decoder that can map the full 1 MB (or 16 MB) address space into dozens of chip-select regions. Its 132 I/O pins handle wide address-and-control buses directly, and the 20 ns tPD provides two-level decode within a single 8 MHz bus cycle without wait-state insertion. The instant-on EEPROM configuration means decoded chip-selects are valid at the first rising edge of the system clock after power-up - critical for legacy CPUs that fetch the reset vector before any software runs. JTAG boundary-scan verifies every decoded output during manufacturing test, eliminating bed-of-nails fixtures.

🌐

Telecom Backplane Bus Interface Bridging

The EPM9320RC208-20's 132 I/O pins and 5 V tolerance allow it to bridge between legacy TTL buses (e.g., H.110 CT-bus, SCSA, parallel TDM) and modern FPGAs in telecom line cards. It performs level conditioning, parity generation/checking, and protocol conversion at the backplane edge, isolating the higher-density downstream FPGA from bus contention. The 20 ns tPD is sufficient for 50 MHz backplane operation when used as a pipeline-stage register, and the IEEE 1149.1 JTAG chain integrates seamlessly with the board's existing boundary-scan test infrastructure. Non-volatile EEPROM configuration means the bridge comes up correctly even after a brownout or hot-swap event, which is essential for NEBS-compliant telecom equipment.

🔧

State-Machine Replacement in Test & Measurement

Test-and-measurement instruments use the EPM9320RC208-20 to implement complex sequencing state machines - scan-chain controllers, multiplexer switching matrices, calibration sequencers - that would otherwise consume dozens of 74LS / 74HC flip-flops. Its 320 macrocells encode multi-state machines with 8 to 10 bits of state plus dozens of transition outputs, all running at deterministic 20 ns latency that keeps stimulus timing reproducible. The 132 I/O pins drive front-panel relays, ADC mux gates, and status LEDs directly without buffer logic. Because the design is stored in on-chip EEPROM, instruments boot into the correct test sequence even in factory-floor environments where power is cycled frequently.

🌐

Peripheral Control Logic in Networking Equipment

Routers, switches, and media gateways use the EPM9320RC208-20 to consolidate PHY interface glue logic - MDIO bus multiplexing, LED status driving, SFP module presence detect, and packet-classifier pre-processing. Its 5 V I/O compatibility matches the levels used by many legacy PHYs, and the 20 ns propagation delay easily handles the 25 MHz MDC clock. The 320 macrocells encode enough state to drive 24+ SFP cage presence/LED signals plus interrupt-aggregation logic in a single chip. JTAG boundary-scan over all 132 I/Os accelerates board bring-up by detecting solder bridges and open pins during in-circuit test, which is critical when each line card carries dozens of high-density connectors.

⚡

Safety-Critical Power-On Control Logic

The EPM9320RC208-20's instant-on non-volatile EEPROM behavior makes it ideal for power-on sequencing and watchdog logic in safety-critical systems (medical devices, industrial PLCs, railway signaling). Unlike SRAM FPGAs that require milliseconds of configuration time, this CPLD drives valid outputs within nanoseconds of VCC crossing 4.75 V, ensuring that reset vectors, watchdog strobes, and power-rail enables are present before any downstream host CPU or DSP boots. Its 320 macrocells encode dozens of independent sequencer channels, and the 132 I/O pins drive housekeeping signals directly. The deterministic 20 ns tPD simplifies worst-case timing analysis required by IEC 61508 SIL-2/3 functional-safety documentation.

What is the propagation delay of the EPM9320RC208-20?
The EPM9320RC208-20 has a maximum pin-to-pin propagation delay (tPD) of 20 ns as indicated by its -20 speed-grade suffix. This delay is deterministic across all macrocell-to-macrocell paths because the MAX 9000 architecture uses a fixed interconnect matrix rather than the variable-length routing found in SRAM FPGAs, making the part well-suited for asynchronous glue-logic where worst-case timing must be predictable.
How many macrocells and I/O pins does the EPM9320RC208-20 have?
The EPM9320RC208-20 integrates 320 macrocells organized in 20 Logic Array Blocks (LABs) and exposes 132 user I/O pins. The part is built from approximately 6,000 usable gates of CMOS EEPROM-based programmable logic. According to the MAX 9000 family datasheet, these resources place it at the high end of the MAX 9000 CPLD density range, suitable for replacing several PAL/GAL devices with a single instant-on non-volatile chip.
What supply voltage does the EPM9320RC208-20 require?
The EPM9320RC208-20 operates from a single 5.0 V supply in the 4.75 V to 5.25 V range (VCCINT). The I/O banks are 5 V TTL/CMOS-compatible within this supply window. Because the device is built on a 5.0 V EEPROM process, it cannot be migrated directly to 3.3 V systems without level shifters, but it integrates cleanly into legacy 5 V industrial and telecom designs that are difficult to migrate to modern low-voltage CPLDs.
Is the EPM9320RC208-20 still in production?
The EPM9320RC208-20 is listed as obsolete in current distributor catalogs and has migrated to last-time-buy status with several authorized resellers. Inventory exists in the secondary market at distributors such as Heisener, Vyrian, and Nantian. The part is now supported by Intel (which acquired Altera's programmable solutions group), and legacy design support is provided through MAX+PLUS II and Quartus II with legacy device support enabled.
What is the difference between EPM9320RC208-20 and EPM9320RC208-15?
The EPM9320RC208-20 (20 ns) and EPM9320RC208-15 (15 ns) share the same 208-pin RQFP package, the same 320-macrocell / 132-I/O MAX 9000 die, and identical 5 V EEPROM ISP architecture. The only difference is speed grade: -15 has a 5 ns faster tPD. The faster part typically costs more and consumes slightly more dynamic current; choose the -20 for cost-sensitive designs where 20 ns timing is acceptable.
EPM9320RC208-20 vs EPM9320ARC208-7 - which is faster?
The EPM9320RC208-20 has a 20 ns tPD while the EPM9320ARC208-7 is a 7 ns speed grade in the same MAX 9000 family. Both share the 208-RQFP package and the same 320-macrocell die, so they are pin-to-pin compatible. The -7 grade is preferred for high-speed address decoding or high-frequency state machines, while the -20 is chosen for lower-cost, moderate-speed glue-logic replacement.
What is the best drop-in replacement for the EPM9320RC208-20?
The most direct drop-in replacements are other MAX 9000 -speed-grade variants in the same 208-RQFP package - the EPM9320RC208-15 and EPM9320RC208-12 differ only in tPD and drop onto the same footprint with no PCB changes required. For a faster device in the identical package, the EPM9320ARC208-7 is also pin-compatible. Always verify your design timing closure at the new speed grade before substituting.
Can a newer MAX II or MAX V CPLD replace the EPM9320RC208-20?
Newer MAX II (EPM240, EPM570, EPM1270) and MAX V (5M80ZE64, 5M160ZE64) CPLDs from Intel/Altera are NOT drop-in replacements because they use different packages (typically 64- or 100-pin EQFP) and operate from 3.3 V or 1.8 V core supplies. A board redesign is required. The migration path keeps the same JTAG ISP programming model and Quartus toolchain, but you cannot place a MAX II directly on a 208-RQFP land pattern.
Where can I download the EPM9320RC208-20 datasheet PDF?
The official MAX 9000 family datasheet is hosted at the Intel Programmable Solutions Group website at intel.com/content/dam/www/programmable/us/en/pdfs/literature/ds/m9000.pdf - this PDF covers all package and speed-grade variants including the EPM9320RC208-20. Legacy design files and BSDL files are also available through the Quartus II legacy device support package for engineers who must continue to use this obsolete part.
What is the pinout configuration of the EPM9320RC208-20?
The EPM9320RC208-20 uses a 208-pin RQFP (also called 208-BFQFP with exposed thermal pad) package. The pinout includes 132 user I/O pins, dedicated JTAG pins (TCK, TMS, TDI, TDO, TRST), power pins (VCCINT, VCCIO), and ground pins distributed around the perimeter. Refer to the MAX 9000 family datasheet pin tables for the exact pin-by-pin assignment - the exposed pad on the package underside must be soldered to the PCB ground plane for thermal dissipation.
How much does the EPM9320RC208-20 cost?
As of 2026-09-13, distributor pricing for the EPM9320RC208-20 ranges from approximately USD 38.50 at qty-1 down to USD 21.90 at qty-1000 on the spot market, reflecting its obsolete status. Stock at authorized distributors is limited; Heisener, Vyrian, Nantian, and Xecor typically list inventory but lead times vary. For new designs, request a quote directly because the secondary-market price fluctuates significantly based on wafer supply.
Is the EPM9320RC208-20 RoHS compliant?
RoHS compliance status for the EPM9320RC208-20 is marked as unknown in current distributor data because the part predates widespread RoHS conversion requirements and was originally released in lead-finish packages. Some later-assembly variants carry lead-free finishes; engineers should request a specific RoHS certificate from the supplier for each lot. Modern MAX II / MAX V replacements are fully RoHS-compliant if RoHS is mandatory for the end product.
What are the key specifications of EPM9320RC208-20 that engineers should know?
The EPM9320RC208-20 is a 5 V, 320-macrocell, 132-I/O, 20 ns MAX 9000 CPLD in a 208-RQFP exposed-pad package with in-system programmability via IEEE 1149.1 JTAG. It is built on CMOS EEPROM technology (instant-on, non-volatile, unlimited reprogram cycles) and operates over the commercial 0 °C to 70 °C range. According to the MAX 9000 datasheet, it provides approximately 6,000 usable gates and is intended for 5 V glue-logic, address decoding, bus-interface bridging, and state-machine replacement in industrial and telecom designs.
What is the lead time for the EPM9320RC208-20?
Lead time for the EPM9320RC208-20 from secondary-market distributors is typically 3 to 7 business days for in-stock parts and 2 to 6 weeks for special orders, depending on distributor and quantity. Heisener currently estimates delivery of August 13-18 for in-stock pieces as of 2026-09-13. Because the part is obsolete, expect limited inventory visibility and consider qualifying an alternative MAX 9000 speed grade or a board redesign to MAX II for long-term supply assurance.

Données de référence d'ingénierie pour EPM9320RC208-20 — comparaison, recommandations de conception et informations de conformité.

Guide de sélection

Choose the EPM9320RC208-20 when you need a 5 V, instant-on non-volatile CPLD with 320 macrocells and 132 I/O for legacy glue-logic consolidation in commercial-temperature (0 °C to 70 °C) industrial or telecom equipment, and the design does not require sub-20 ns propagation delay. Choose the EPM9320RC208-15 or -12 if your design has 30-40 MHz bus interfaces where 15 ns tPD provides margin. Choose the EPM9320ARC208-10 for high-speed address decoding at 50 MHz or above. All of these share the same 208-RQFP footprint, so a PCB redesign is not required when changing speed grades. For new designs, consider migrating to MAX II (EPM570) or MAX V (5M160ZE64) CPLDs - they require a PCB change to a smaller EQFP package and 3.3 V supply, but they offer lower power and active Intel support.

Comparaison avec les alternatives

Paramètre Ce produit EPM9320RC208-15 EPM9320RC208-15N EPM9320RC208-10 EPM9320ARC208-10
Brand Altera (Intel) Altera (Intel) Altera (Intel) Altera (Intel) Altera (Intel)
Package 208-RQFP (exposed pad) 208-RQFP (exposed pad) - same 208-RQFP (exposed pad) - same 208-RQFP (exposed pad) - same 208-RQFP (exposed pad) - same
Macrocells 320 320 320 320 320
Max I/O 132 132 132 132 132
Propagation Delay (tPD max) 20 ns 15 ns (faster) 15 ns (faster) 10 ns (faster) 10 ns (faster)
Supply Voltage 4.75 V to 5.25 V 4.75 V to 5.25 V 4.75 V to 5.25 V 4.75 V to 5.25 V 4.75 V to 5.25 V
Programming Technology EEPROM (ISP via JTAG) EEPROM (ISP via JTAG) EEPROM (ISP via JTAG) EEPROM (ISP via JTAG) EEPROM (ISP via JTAG)
Operating Temperature 0 °C to 70 °C 0 °C to 70 °C 0 °C to 70 °C 0 °C to 70 °C 0 °C to 70 °C
Lifecycle Status Obsolete Obsolete (same family) Obsolete (same family) Obsolete (same family) Obsolete (same family)

Principaux différenciateurs

  • Slowest speed grade in the EPM9320RC208 family, lowest secondary-market cost (vs EPM9320RC208-15)
  • 320-macrocell density vs lower-end MAX 7000S family members (vs EPM7256SQC208-10)
  • MAX 9000 EEPROM instant-on vs MAX II SRAM configuration delay (vs EPM240T100C5N (MAX II))

Notes de conception

Solder the exposed thermal pad on the underside of the 208-RQFP package to a PCB ground plane with at least 1 square inch (645 mm²) of copper area. The MAX 9000 device dissipates roughly 1.5 W at 100% macrocell utilization at 5 V, and without the thermal pad soldered junction temperature can exceed 100 °C even at room ambient. Estimate: at 1.5 W with 1 sq-in. copper pour, θJA ≈ 18 °C/W yields a 27 °C rise above 25 °C ambient (52 °C junction), well within the 70 °C commercial ceiling. For sealed industrial enclosures above 50 °C ambient, expand the copper area to 2-3 sq-in. or add forced-air cooling.

Decouple every VCC pin with a 0.1 µF ceramic capacitor placed within 3 mm (0.12 in.) of the supply pin and tie the GND return directly to the inner ground plane via a short via. Add one bulk 10 µF tantalum or aluminum-polymer capacitor near the corner of the package to handle simultaneous-switching-output (SSO) current transients from the 132 I/O pins. Place the JTAG TCK trace away from the I/O banks and add a 10 kΩ pull-up on TMS and TDI, plus a 10 kΩ pull-down on TRST to keep the boundary-scan state machine in known state during power-up.

Do not exceed 5.25 V on VCCINT even momentarily - the EEPROM programming circuits can latch-up above 6 V. Do not leave unused I/O pins floating; configure them in MAX+PLUS II / Quartus as outputs driving '0' or as inputs with internal pull-ups enabled, otherwise floating inputs draw 10-100 µA each and increase total quiescent current. Verify JTAG chain order in BSDL files when multiple MAX devices share one TCK/TMS bus - a reversed chain will pass boundary-scan tests but fail ISP programming. Finally, allow at least 50 ms after VCC stabilizes before initiating JTAG operations because the EEPROM charge pump requires settling time.

Informations de conformité

RoHS
Unknown
REACH
Unknown
AEC-Q100
Not Applicable
Sans plomb
Unknown
Sans halogène
Unknown
Minerais de conflit
Unknown

EPM9320RC208-20 predates widespread RoHS conversion requirements; compliance depends on the specific date code and assembly variant. Standard Altera lead-finish parts carry SnPb solder, while lead-free variants (suffix 'N' such as EPM9320RC208-15N) are RoHS-compliant. Request specific compliance certificates from the supplier for each lot. Not AEC-Q100 qualified (industrial/consumer grade only).

Données vérifiées le : 2026-09-13 — données vérifiées et sélectionnées par l'équipe d'ingénierie composants de XAIPART

Recherches associées

EPM9320RC208-20 EPM9320RC208-20 datasheet Altera MAX 9000 CPLD 320 macrocell CPLD 5V 208-pin RQFP exposed pad CPLD EPM9320RC208-20 drop-in replacement EPM9320RC208-20 vs EPM9320RC208-15 5V glue logic CPLD JTAG ISP EPM9320RC208-20 buy price stock MAX 9000 family datasheet PDF obsolete Altera CPLD replacement what is the propagation delay of EPM9320RC208-20 EPM9320RC208-20 pinout 208-RQFP CPLD address decoder 5V industrial

Composants & termes associés

Altera Intel EPM9320RC208-20 EPM9320RC208-15 EPM9320RC208-15N EPM9320RC208-10 EPM9320ARC208-10 EPM9320ARI208-10 EPM9320GC280-20 MAX 9000 CPLD Complex Programmable Logic Device Multiple Array Matrix (MAX) macrocell Logic Array Block (LAB) EEPROM in-system programmability (ISP) IEEE 1149.1 JTAG boundary-scan RQFP-208 BFQFP exposed thermal pad surface mount 5.0 V CMOS glue logic address decoding MAX+PLUS II Quartus II RoHS AEC-Q100 industrial control telecom equipment test and measurement
RFQ de devis rapide
Renseignez tous les détails — notre équipe commerciale vous répondra sous 24 heures
Référence Fabricant Boîtier QTY Prix cible Total
Total : 0,00 USD
✓
Devis envoyé !

Nous répondrons à votre e-mail sous 24 heures

1
RFQ envoyée
2
Devis reçu
3
Commande passée
4
Paiement
5
Expédié
6
Livré
Voir les détails de la RFQ