Altera

EPM9560RC208-19 - MAX 9000 CPLD, 560 Macrocells, 19ns | Altera

Référence : EPM9560RC208-19 ✗ Fin de vie

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5.0 V Vdss RQFP-208 (208-pin PQFP) Package

À partir de $16.2 USD / unité

MOQ : 1 |

Prix mis à jour : 2026-09-13

Tarifs dégressifs

Qté	Prix unitaire	Total
1	$28.5	$28,50
10	$24.95	$249,50
100	$21.4	$2 140,00
500	$18.75	$9 375,00
1 000	$16.2	$16 200,00

ℹ️ Tous les prix sont en USD

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EPM9560RC208-19 Présentation

The Altera EPM9560RC208-19 is a high-performance CMOS EEPROM-based Complex Programmable Logic Device (CPLD) from the MAX 9000 device family, featuring 560 macrocells, 12,000 usable gates, and a pin-to-pin propagation delay of 19 ns, housed in a 208-pin RQFP package. Built on Altera's third-generation Multiple Array MatriX (MAX) architecture, the device provides 5.0-V in-system programmability (ISP) through a built-in IEEE Std. 1149.1 JTAG interface, enabling boundary-scan test, in-system configuration, and rapid prototyping without external programmers.

A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that combines the architectural simplicity of PAL/GAL with high-density macrocell fabric and deterministic timing. Within the broader programmable logic hierarchy, CPLDs sit below FPGAs in density but above simple PLDs in logic capacity, offering instant-on behavior, single-chip solutions, and predictable routing delays that make them ideal for glue logic, bus interface, and state-machine replacement roles.

Key features of the EPM9560RC208-19 include 772 flip-flops, 149 user I/O pins, 5-V tolerant I/O with multi-voltage interface support, JTAG-compliant ISP, and a maximum toggle frequency that supports high-speed control logic. The 208-pin RQFP (also called PQFP) package provides a generous I/O count for system integration while retaining a manageable footprint for production assembly. The -19 speed grade designates the 19 ns propagation delay bin.

Technical depth: the MAX 9000 architecture uses a programmable interconnect array (PIA) that routes signals between Logic Array Blocks (LABs), giving every signal a consistent and predictable delay regardless of placement. This deterministic timing eliminates the place-and-route iterations often required by FPGAs. The EEPROM-based configuration cell is non-volatile, so the device powers up instantly in its programmed state with no external boot memory required.

Typical applications include bus interfacing (PCI, ISA, VME), state-machine replacement, address decoding and glue logic in microprocessor systems, peripheral control, and high-volume glue-logic consolidation. The wide I/O count makes it particularly suited to 32-bit and 64-bit system bus bridging tasks.

Design consideration: when migrating a MAX 9000 design to a newer family, verify that the pinout and JTAG programming flow are compatible. The RQFP-208 footprint differs from later BGA-packaged MAX II/MAX V devices, so PCB redesign is generally required.

This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet alone, providing engineers with a single reference for the EPM9560RC208-19 across sourcing, design, and lifecycle decisions.

Alternatives de remplacement direct pour EPM9560RC208-19 — même boîtier, compatible broche à broche. Les références à boîtier différent nécessitant une retouche du PCB sont exclues.

Variantes de cette série

Modèles de la même série directement compatibles avec EPM9560RC208-19 (même facteur de forme et même empreinte) — différant par Package, Device Type, Propagation Delay (tPD), Configuration Memory, User I/O Pins.

EPM9560RC208-15

Altera

Package: 208-pin RQFP (Power Quad Flat Pack)

Device Type: EEPROM-based Complex Programmable Logic Device (CPLD)