EP910PC-35 vs EP910DC-35 Perbandingan
Perbandingan bersamaan detil EP910PC-35 dari Altera dan EP910DC-35 dari Altera. Bandingkan spesifikasi penting, parameter listrik, pengemasan, status cycle, harga, dan ketersediaan untuk menentukan komponen terbaik untuk kebutuhan desain Anda.
Perbandingan Spesifikasi
| Parameter Umum | EP910PC-35 | EP910DC-35 |
|---|---|---|
| Merek | Altera | Altera |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Status Lingkungan Hidup | Obsolete | Obsolete |
| Family | Classic EPLD | Classic EPLD EP910 |
| Device Type | EPLD (Erasable Programmable Logic Device) | UV-Erasable CMOS PLD (PAL-type) |
| Macrocells | 24 | 24 |
| I/O Pins | 24 | 24 |
| Dedicated Inputs | 12 | 12 |
| Total Inputs | 36 | 36 |
| Product Terms | 240 | 240 |
| Propagation Delay (tPD) | 35 ns | — |
| Maximum Counter Frequency | 37 MHz | — |
| Internal Performance Frequency | 100 MHz | — |
| Technology | CMOS, UV-erasable/OTP | CMOS, UV-erasable EPROM cell |
| Tegangan Pemuat | 5 V | — |
| Suhu Kerja | [DATA_NEEDED: operating temperature range] | 0 °C to +70 °C (commercial) |
| Paket | 40-pin PDIP (Plastic DIP) | 40-pin CDIP (Ceramic DIP) with quartz window |
| Tipe Mounting | Through-Hole | — |
| Architecture | PAL-type sum-of-products, AND/OR array | PAL-type sum-of-products AND-OR array |
| Programming Method | UV-erase (ceramic) / OTP (plastic), A+PLUS / MAX+PLUS tools | JEDEC fuse map via device programmer; UV erase |
| Compliance / RoHS | [DATA_NEEDED: RoHS status - legacy part] | — |
| Usable Gates | — | 900 gates |
| Propagation Delay (tpd) | — | 35 ns |
| Frekuensi Bawah Maximum | — | 37 MHz (typical, internal) |
| Supply Voltage (Vcc) | — | 4.75 V to 5.25 V (5 V nominal) |
| Lead Pitch | — | 2.540 mm |
| Termination Style | — | Through-Hole |
| Status RoHS | — | Non-compliant (ceramic DIP with Pb-bearing lead finish) |
| Lifecycle | — | Obsolete / last-time-buy from authorized distributors |