EP910PC-35 vs EP910DC-35 比較
詳細並排比較 EP910PC-35 由 Altera 與 EP910DC-35 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP910PC-35 | EP910DC-35 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | Classic EPLD | Classic EPLD EP910 |
| Device Type | EPLD (Erasable Programmable Logic Device) | UV-Erasable CMOS PLD (PAL-type) |
| Macrocells | 24 | 24 |
| I/O Pins | 24 | 24 |
| Dedicated Inputs | 12 | 12 |
| Total Inputs | 36 | 36 |
| Product Terms | 240 | 240 |
| Propagation Delay (tPD) | 35 ns | — |
| Maximum Counter Frequency | 37 MHz | — |
| Internal Performance Frequency | 100 MHz | — |
| Technology | CMOS, UV-erasable/OTP | CMOS, UV-erasable EPROM cell |
| 供應電壓 | 5 V | — |
| 工作溫度 | [DATA_NEEDED: operating temperature range] | 0 °C to +70 °C (commercial) |
| 封裝 | 40-pin PDIP (Plastic DIP) | 40-pin CDIP (Ceramic DIP) with quartz window |
| 安裝類型 | Through-Hole | — |
| Architecture | PAL-type sum-of-products, AND/OR array | PAL-type sum-of-products AND-OR array |
| Programming Method | UV-erase (ceramic) / OTP (plastic), A+PLUS / MAX+PLUS tools | JEDEC fuse map via device programmer; UV erase |
| Compliance / RoHS | [DATA_NEEDED: RoHS status - legacy part] | — |
| Usable Gates | — | 900 gates |
| Propagation Delay (tpd) | — | 35 ns |
| 最大時脈頻率 | — | 37 MHz (typical, internal) |
| Supply Voltage (Vcc) | — | 4.75 V to 5.25 V (5 V nominal) |
| Lead Pitch | — | 2.540 mm |
| Termination Style | — | Through-Hole |
| RoHS 狀態 | — | Non-compliant (ceramic DIP with Pb-bearing lead finish) |
| Lifecycle | — | Obsolete / last-time-buy from authorized distributors |