EP910PC-35 vs EP910DC-35 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EP910PC-35 sa pamamagitan ng Altera at EP910DC-35 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EP910PC-35 EP910DC-35
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Obsolete
Family Classic EPLD Classic EPLD EP910
Device Type EPLD (Erasable Programmable Logic Device) UV-Erasable CMOS PLD (PAL-type)
Macrocells 24 24
I/O Pins 24 24
Dedicated Inputs 12 12
Total Inputs 36 36
Product Terms 240 240
Propagation Delay (tPD) 35 ns —
Maximum Counter Frequency 37 MHz —
Internal Performance Frequency 100 MHz —
Technology CMOS, UV-erasable/OTP CMOS, UV-erasable EPROM cell
Volte ng Pagbibigay 5 V —
Temperature na Operasyon [DATA_NEEDED: operating temperature range] 0 °C to +70 °C (commercial)
Packhaging 40-pin PDIP (Plastic DIP) 40-pin CDIP (Ceramic DIP) with quartz window
Uri ng Pagpapasok Through-Hole —
Architecture PAL-type sum-of-products, AND/OR array PAL-type sum-of-products AND-OR array
Programming Method UV-erase (ceramic) / OTP (plastic), A+PLUS / MAX+PLUS tools JEDEC fuse map via device programmer; UV erase
Compliance / RoHS [DATA_NEEDED: RoHS status - legacy part] —
Usable Gates — 900 gates
Propagation Delay (tpd) — 35 ns
Maksimum na Taktiko ng Oras — 37 MHz (typical, internal)
Supply Voltage (Vcc) — 4.75 V to 5.25 V (5 V nominal)
Lead Pitch — 2.540 mm
Termination Style — Through-Hole
Tindminan RoHS — Non-compliant (ceramic DIP with Pb-bearing lead finish)
Lifecycle — Obsolete / last-time-buy from authorized distributors

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