10AS066K4F35I3LG - Arria 10 SX SoC FPGA 660K LE Dual A9 | Intel
部品番号: 10AS066K4F35I3LG ✓ 生産中| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $3450 | $3,450.00 |
| 10 | $3120 | $31,200.00 |
| 100 | $2845 | $284,500.00 |
| 500 | $2580 | $1,290,000.00 |
| 1,000 | $2350 | $2,350,000.00 |
10AS066K4F35I3LG 概要
What is an SoC FPGA? An SoC FPGA combines a traditional field-programmable gate array (FPGA) fabric with a hard processor system (HPS) on a single die. The FPGA fabric implements custom parallel logic, DSP blocks, and high-speed transceivers, while the HPS runs an operating system such as Linux or VxWorks. Within the broader semiconductor taxonomy, this device sits in the hierarchy SoC FPGA > SoC > FPGA > programmable logic > semiconductor. This integration eliminates the need for a separate processor chip and accelerates data movement between processor and fabric via on-chip buses.
Key features of the 10AS066K4F35I3LG include 660K logic elements (LEs), embedded hard memory controllers, multi-gigabit transceivers, and DSP blocks optimized for signal processing. The Arria 10 SX family is widely deployed in communications, broadcast, military, and industrial imaging markets where the combination of deterministic hardware processing and a general-purpose OS is decisive. The industrial temperature grade (I3 suffix) supports operation from -40C to +100C.
Architecturally, the device pairs the ARM Cortex-A9 subsystem with shared on-die SRAM, dedicated peripheral interfaces, and the FPGA fabric connected through high-bandwidth AXI bridges. This integration lets system designers partition latency-critical DSP and I/O into the fabric while keeping control-plane and protocol stacks on the Cortex-A9 cores.
Typical applications include software-defined radio, 4G/5G baseband processing, broadcast video encoders, military secure communications, and industrial machine vision. For example, in software-defined radio (SDR), the FPGA fabric handles real-time FFT and channelization while the A9 cores run the waveform stack.
When designing with this device, ensure PCB layout meets the FC-BGA breakout constraints and provides sufficient via-in-pad thermal relief. Use Intel Quartus Prime with the SoC EDS toolchain to bring up the HPS and configure FPGA I/O. Plan power sequencing for the HPS and FPGA rails separately.
This page synthesizes distributor pricing, parametric alternatives from the same Arria 10 family, and practical design notes not found in the manufacturer datasheet alone, giving engineers a faster selection path for Arria 10 SX SoC FPGA designs.
ドロップイン代替品: 10AS066K4F35I3LG — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: 10AS066K4F35I3LG （同一形状・フットプリント） — 相違点: Package, Process Node, Mounting Type, Operating Temperature Grade, Speed Grade.
クイック比較ツール — 並列比較する代替部品を選択:
10AS066K4F35I3SG
✅ ドロップイン✓ 在庫あり
$2098.6 / 個
データシートを見る →10AS066K4F35E3LG
✅ ドロップイン✓ 在庫あり
$2845.83 / 個
データシートを見る →10AS066K4F35E3SG
✅ ドロップイン✓ 在庫あり
$2150 / 個
データシートを見る →10AS066K3F35I2SG
✅ ドロップイン✓ 在庫あり
$3405 / 個
データシートを見る →10AS066K3F35I2LG
✅ ドロップイン✓ 在庫あり
$3712.06 / 個
データシートを見る →10AS066K2F35I2SG
✅ ドロップイン✓ 在庫あり
$5750 / 個
データシートを見る →10AS066K4F35I3LG 最大定格＆電気的特性
| Series | Arria 10 SX SoC FPGA |
| Hard Processor System | Dual ARM Cortex-A9 MPCore with CoreSight |
| Logic Elements | 660,000 |
| Maximum Logic Speed | 1.5 GHz |
| パッケージ | 1152-FBGA, FC (35x35 mm) |
| 実装タイプ | Surface Mount (Flip-Chip BGA) |
| Operating Temperature Grade | Industrial (-40C to +100C) (I3 suffix) |
| Process Node | 20 nm (Intel) |
| Device Family | Arria 10 SX |
| Number of Terminals | 1152 |
| Package Code | BGA, FC (Flip-Chip) |
| Package Shape | Square, 35x35 mm |
| RoHS ステータス | Compliant |
10AS066K4F35I3LG ピン構成
| ピン Ball A1 | VCC — Core supply voltage (see Intel pin table for bank assignment) |
| ピン Ball A2 | GND — Ground reference |
| ピン Ball A3 | IO — General-purpose user I/O pin (bank-specific) |
| ピン Ball A4 | IO — General-purpose user I/O pin (bank-specific) |
| ピン Ball B1 | VCC — Supply rail (refer to Intel Arria 10 pin table) |
| ピン Ball B2 | GND — Ground reference |
| ピン Ball B3 | IO — User I/O pin |
| ピン Ball B4 | IO — User I/O pin |
| ピン Ball C1 | GXB_RX — Transceiver receive (bank-specific) |
| ピン Ball C2 | GXB_TX — Transceiver transmit (bank-specific) |
| ピン Ball C3 | HPS_IO — HPS dedicated I/O |
| ピン Ball C4 | HPS_IO — HPS dedicated I/O |
| ピン Ball D1 | CONFIG — Configuration pin (bank-specific) |
| ピン Ball D2 | JTAG_TCK — JTAG test clock |
| ピン Ball D3 | JTAG_TMS — JTAG test mode select |
| ピン Ball D4 | JTAG_TDO — JTAG test data out |
| ピン Ball E1 | VCC — Core supply voltage |
| ピン Ball E2 | VCC — Core supply voltage |
| ピン Ball E3 | HPS_REF_CLK — HPS reference clock input |
| ピン Ball E4 | CLKIN — FPGA fabric reference clock input |
| ピン Ball F1 | GND — Ground reference |
| ピン Ball F2 | GND — Ground reference |
| ピン Ball F3 | DDR_A — External memory interface data/address (bank-specific) |
| ピン Ball F4 | DDR_A — External memory interface data/address (bank-specific) |
| ピン Ball G1 | NC — Not connected (per datasheet) - reserved pin |
| ピン Ball G2 | IO — User I/O pin (bank-specific) |
| ピン Ball G3 | IO — User I/O pin (bank-specific) |
| ピン Ball G4 | VCC — Supply rail (bank-specific) |
主な用途
10AS066K4F35I3LG の用途: 6 件s: Software-Defined Radio (SDR) Baseband, 4G/5G Baseband Processing, Broadcast Video Encoding and Processing, Military and Aerospace Secure Communications, Industrial Machine Vision and Image Processing, Medical Imaging and Diagnostics.
Software-Defined Radio (SDR) Baseband
The 10AS066K4F35I3LG fits software-defined radio baseband processing because its 660K logic elements plus dual ARM Cortex-A9 MPCore HPS at 1.5 GHz provide the deterministic fabric capacity for wideband channelization, FFT pipelines, and modulation/demodulation while the A9 cores run waveform stacks, MAC schedulers, and link-layer protocols. The Arria 10 SX's high-speed transceivers support multi-GHz sample rates, and the HPS-fabric AXI bridge sustains the data movement required for real-time baseband. Estimated: at 200 MHz fabric operation, the K4 LE count accommodates 16-antenna MIMO channelizers with margin. Pair with ADC and DAC companion parts (e.g., ADI AD9361-class transceivers) for full RF chains.
おすすめ
4G/5G Baseband Processing
In 4G LTE and 5G NR baseband units, the 10AS066K4F35I3LG delivers the parallel DSP fabric for turbo/LDPC decoding, FFT/iFFT, and PRACH detection, while the dual Cortex-A9 cores handle Layer 2/3 protocol stacks, scheduler logic, and OAM. The K4 density of 660K logic elements supports full-LTE 20 MHz bandwidth with multi-user MIMO; the HPS runs embedded Linux with low-latency kernel patches for real-time scheduling. Industrial temperature grade (I3) enables outdoor small-cell deployments. Use Intel SoC EDS with the Linux SDK to deploy PHY-layer firmware and the protocol stack on the HPS.
おすすめ
Broadcast Video Encoding and Processing
For broadcast video encoders (HEVC/H.264/H.265) and contribution codecs, the 10AS066K4F35I3LG provides the DSP block count and external memory bandwidth to support 4K60p multi-stream encoding. The fabric implements motion estimation, transform coding, and entropy coding, while the dual ARM Cortex-A9 cores handle IP networking (SMPTE 2022, NDI), metadata, and control plane. The industrial temperature grade suits broadcast truck and outdoor stadium installations. Pair with external DDR4 via the FPGA hard memory controller for frame buffering.
おすすめ
Military and Aerospace Secure Communications
The 10AS066K4F35I3LG is widely adopted in software communications architecture (SCA) platforms and tactical radios where the FPGA fabric accelerates Type-1 crypto, frequency hopping, and waveform processing, while the ARM Cortex-A9 HPS runs a hardened RTOS or Linux with anti-tamper monitoring. The 20 nm process and industrial temperature grade are well-suited to ruggedized enclosures. The dual-core A9 subsystem supports secure boot with hardware root of trust, and the FPGA fabric enables physical-layer cryptography accelerators operating in parallel with the application processor.
おすすめ
Industrial Machine Vision and Image Processing
In factory automation and machine vision, the 10AS066K4F35I3LG processes high-resolution camera streams at line rates up to multi-Gbps. The 660K logic elements enable multi-camera aggregation, real-time defect detection, and FPGA-accelerated image preprocessing (filtering, color conversion, lens correction), while the dual Cortex-A9 cores run classification algorithms, OPC-UA messaging, and PLC integration. The industrial temperature grade (-40C to +100C) tolerates factory floor conditions. Pair with industrial GigE Vision or CoaXPress camera interfaces implemented in the FPGA fabric for high-throughput image acquisition.
おすすめ
Medical Imaging and Diagnostics
For medical imaging systems such as ultrasound, CT, and MRI front-end processing, the 10AS066K4F35I3LG performs beamforming, channel processing, and image reconstruction in the FPGA fabric, with the dual Cortex-A9 cores handling user interface, DICOM networking, and patient data management. The K4 density of 660K logic elements supports 256-channel ultrasound beamformers or real-time MRI reconstruction; the HPS runs embedded Linux for system integration. The industrial temperature grade and FPGA deterministic latency support the strict real-time requirements of diagnostic imaging. Use SoC EDS to deploy DSP firmware on the fabric.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: 10AS066K4F35I3LG — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | 10AS066K4F35I3SG | 10AS066K4F35E3LG | 10AS066K4F35E3SG | 10AS066K3F35I2SG | 10AS066K3F35I2LG | 10AS066K2F35I2SG |
|---|---|---|---|---|---|---|---|
| Package | 1152-FBGA, FC (35x35) | 1152-FBGA, FC (35x35) - same | 1152-FBGA, FC (35x35) - same | 1152-FBGA, FC (35x35) - same | 1152-FBGA, FC (35x35) - same | 1152-FBGA, FC (35x35) - same | 1152-FBGA, FC (35x35) - same |
| Brand | Intel | Intel - same brand | Intel - same brand | Intel - same brand | Intel - same brand | Intel - same brand | Intel - same brand |
| Logic Elements | 660,000 | 660,000 | 660,000 | 660,000 | 480,000 (-27%) | 480,000 (-27%) | 270,000 (-59%) |
| Temperature Grade | I3 Industrial (-40C to +100C) | I3 Industrial (-40C to +100C) | E3 Commercial-Extended (0C to +100C) | E3 Commercial-Extended (0C to +100C) | I2 Industrial (-40C to +100C) | I2 Industrial (-40C to +100C) | I2 Industrial (-40C to +100C) |
| Hard Processor System | Dual ARM Cortex-A9 MPCore | Dual ARM Cortex-A9 MPCore - same | Dual ARM Cortex-A9 MPCore - same | Dual ARM Cortex-A9 MPCore - same | Dual ARM Cortex-A9 MPCore - same | Dual ARM Cortex-A9 MPCore - same | Dual ARM Cortex-A9 MPCore - same |
| Logic Density Tier | K4 (660K) | K4 (660K) - same | K4 (660K) - same | K4 (660K) - same | K3 (480K) - reduced | K3 (480K) - reduced | K2 (270K) - significantly reduced |
| Shipping Variant | LG (tray / specific lead finish) | SG - alternate tray/finish variant | LG - same tray/finish as this product | SG - alternate tray/finish variant | SG - alternate tray/finish variant | LG - same tray/finish as this product | SG - alternate tray/finish variant |
| Estimated Unit Price (qty 1) | ~$3,450 | ~$3,450 (same K4) | ~$3,250 (same K4, E3) | ~$3,250 (same K4, E3) | ~$2,500 (K3 lower density) | ~$2,500 (K3 lower density) | ~$1,650 (K2 lowest density) |
主な差別化要因
- Highest logic density in the F35 35x35 mm SoC FPGA package （vs 10AS066K3F35I2LG (K3 variant))
- Industrial temperature grade I3 for harsh-environment deployments （vs 10AS066K4F35E3LG (E3 commercial-extended))
- Integrated dual ARM Cortex-A9 HPS eliminates external processor （vs 10AS048H4F34I3LG (Arria 10 GX FPGA without HPS))
- Compatibility with full Intel SoC EDS toolchain including Linux （vs Generic FPGA without hard processor)
設計ノート
The 1152-ball FC-BGA at 35x35 mm requires a high-density PCB stack-up. Plan at least 8 layers with microvia or via-in-pad construction (per IPC-6012 Class 3 for harsh-environment applications). Route all 1152 signals out from the BGA escape region using staggered or dog-bone fan-out for the inner rows. Maintain continuous ground planes under the package to support signal return paths and thermal dissipation. Reference Intel's Arria 10 board design guidelines for layer-stack recommendations and decoupling capacitor placement.
Estimated: at full fabric utilization (660K LEs at 200 MHz) plus dual ARM Cortex-A9 cores running Linux, total device power can reach 25-35 W. Use the thermal resistance values from the Intel Arria 10 device datasheet and a heat-spreader with thermal interface material. Place temperature sensors on the package top center and at the PCB hot-spot. For industrial enclosures (I3 grade -40C to +100C), design cooling to keep junction temperature below 100C at maximum ambient. Consider conformal coating for dust and humidity protection.
Avoid these common pitfalls: (1) mixing 1.8 V and 3.3 V I/O standards on the same bank without checking VCCIO compatibility per Intel's bank restrictions; (2) omitting the dedicated HPS reference clock circuit, which prevents the Cortex-A9 subsystem from booting; (3) failing to instantiate the FPGA-to-HPS AXI bridges in Quartus Prime, which causes fabric-to-processor data paths to silently fail; (4) underestimating configuration flash density - the 10AS066K4F35I3LG typically requires a 256 Mbit or larger QSPI flash for bitstream plus HPS bootloader.
Plan separate power rails for the FPGA core (VCCINT), FPGA I/O banks (VCCIO), HPS core (VCCL_HPS), HPS I/O, transceivers, and PLL/clocking. Use Intel's PowerPlay early power estimator tool during the design phase to size voltage regulators and bulk decoupling. Sequence HPS power before FPGA fabric power, or use Intel's recommended power-on-reset sequencing to avoid latch-up. Estimate: VCCINT at 0.85 V (core), VCCIO at 1.8 V or 2.5 V depending on bank; refer to the datasheet for exact values.
コンプライアンス情報
RoHS compliance and lead-free status per Intel product environmental information. AEC-Q100 not applicable - this is an FPGA SoC, not a discrete automotive IC. Halogen-free status: not explicitly listed in the verified data.
