10AS066K3F35I2LG - Arria 10 SX SoC FPGA 660K LE 1152-FCBGA | Intel
MPN: 10AS066K3F35I2LG ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $5302.94 | $5,302.94 |
| 10 | $4772.65 | $47,726.50 |
| 100 | $4242.35 | $424,235.00 |
| 500 | $3977.21 | $1,988,605.00 |
| 1,000 | $3712.06 | $3,712,060.00 |
Drop-in alternatives for 10AS066K3F35I2LG — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
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10AS066K3F35I2SG
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View Datasheet →10AS066K3F35E2LG
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View Datasheet →10AS066K3F35E2SG
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View Datasheet →10AS066K2F35I2SG
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View Datasheet →10AS066K2F35E2SG
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View Datasheet →10AS066K3F35I2LG Maximum Ratings & Electrical Characteristics
| Family | Arria 10 SX SoC FPGA |
| Logic Elements | 660,000 |
| Hard Processor System | Dual-core ARM Cortex-A9 MPCore with CoreSight |
| HPS Clock Speed | 1.5 GHz |
| Package | 1152-ball FCBGA (F35), 35x35 mm |
| Process Node | TSMC 20 nm |
| Operating Temperature | -40C to +100C (Industrial) |
| Speed Grade | K3 (mid-speed) |
| Logic Voltage | 0.9 V core |
| Transceiver Data Rate (max) | 28.05 Gbps |
| PCIe Hard IP | PCIe Gen3 x8 hard IP |
| External Memory Support | DDR4, DDR3, LPDDR3, QDR IV, RLDRAM III |
| RoHS Status | Compliant |
| Mounting Type | Surface Mount (FCBGA) |
10AS066K3F35I2LG 1152-ball fcbga (f35), 35x35 mm Pin Configuration Guide
Complete pinout information for 10AS066K3F35I2LG (1152-ball fcbga (f35), 35x35 mm package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for 10AS066K3F35I2LG.
Refer to the datasheet for full pin configuration.
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
10AS066K3F35I2LG is suitable for 6 applications: 5G/LTE Wireless Baseband Processing, Radar and Electronic Warfare Signal Processing, Medical Imaging and Ultrasound Beamforming, Industrial Machine Vision and Inspection, Broadcast Video Processing and Encoding, Military Secure Communications and SDR.
5G/LTE Wireless Baseband Processing
The 10AS066K3F35I2LG's 660K logic elements combined with variable-precision DSP blocks exceed 1 TFLOPS single-precision throughput, making it ideal for 5G small-cell and LTE baseband processing where latency-sensitive PHY-layer operations must complete within microsecond budgets. The dual-core ARM Cortex-A9 HPS at 1.5 GHz runs the MAC scheduler, RRC protocol stack, and OAM telemetry, freeing the FPGA fabric for turbo decoding, FFT/iFFT, and channel estimation. The 28.05 Gbps transceivers support CPRI and eCPRI fronthaul links common in C-RAN radio architectures, eliminating external PHY chips. Place-and-route timing typically closes at 300-400 MHz on DSP-heavy paths in the K3 mid-speed grade.
Recommended
Radar and Electronic Warfare Signal Processing
The 10AS066K3F35I2LG delivers the computational density required for phased-array radar beamforming, pulse compression, and Doppler processing at sub-microsecond latencies. Its 28.05 Gbps transceivers stream ADC samples directly into the FPGA fabric, while the variable-precision DSP blocks perform complex FFTs and matched filtering in real time. The ARM Cortex-A9 HPS handles track management, target classification, and Ethernet/1553 interfaces to higher-level command systems. For electronic warfare applications, the wide FPGA fabric enables simultaneous multiband digital down-conversion and threat-signal characterization within a single SoC, reducing board area and BOM versus discrete architectures.
Recommended
Medical Imaging and Ultrasound Beamforming
The 10AS066K3F35I2LG is widely deployed in ultrasound beamforming carts and portable imaging systems because its 660K logic elements and high-speed DSP throughput align with 64-256 channel beamformer pipelines. The HPS runs the user interface, DICOM stack, and patient database connectivity, while the FPGA fabric handles receive-side delay-and-sum beamforming at kHz channel-update rates. The 1.5 GHz Cortex-A9 cores accelerate post-processing algorithms (speckle reduction, harmonic imaging) and JPEG2000 compression for archival. Industrial temperature grade and RoHS compliance make it suitable for clinical equipment requiring long product lifecycles.
Recommended
Industrial Machine Vision and Inspection
In factory-floor inspection systems, the 10AS066K3F35I2LG's parallel fabric accelerates image preprocessing (filtering, edge detection, FFT-based texture analysis) at line-rate speeds while the ARM Cortex-A9 HPS coordinates with PLCs via EtherCAT or PROFINET, manages the inspection database, and runs anomaly-detection machine-learning inference. The PCIe Gen3 x8 hard IP interfaces to frame grabbers or CoaXPress cameras, and the DDR4 controller handles multi-megapixel image buffering. Industrial temperature grade (-40C to +100C) ensures reliable operation in unconditioned factory environments with thermal cycling and vibration.
Recommended
Broadcast Video Processing and Encoding
The 10AS066K3F35I2LG powers broadcast-grade video processing appliances for HEVC/H.265 encoding, deinterlacing, color-space conversion, and SDI/HDMI/DisplayPort bridging. The FPGA fabric handles real-time video pipelines at 4K60 resolutions, while the HPS runs the web management interface, REST API, and stream multiplexing logic. The 28.05 Gbps transceivers support 12G-SDI for uncompressed 4K video transport, eliminating external serializer/deserializer chips. Broadcast deployments benefit from long Arria 10 product lifecycle support and Intel's FPGA toolchain stability for professional video workflows.
Recommended
Military Secure Communications and SDR
The 10AS066K3F35I2LG integrates programmable logic with a hard ARM Cortex-A9 HPS, making it suitable for software-defined radio platforms running encryption, waveform processing, and protocol stacks in tactical communication systems. The wide FPGA fabric supports wideband channelization, polyphase filter banks, and cryptographic accelerators, while the HPS handles key management and secure boot. The 28.05 Gbps transceivers cover L-band through Ku-band IF sampling and high-speed ADC/DAC interfacing. Industrial temperature grade and long product lifecycle support meet MIL-STD-810G environmental requirements for deployed military systems.
Recommended
Recommended Products Summary
Engineering reference data for 10AS066K3F35I2LG — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | 10AS066K3F35I2SG | 10AS066K3F35E2LG | 10AS066K3F35E2SG | 10AS066K2F35I2LG | 10AS066K2F35I2SG |
|---|---|---|---|---|---|---|
| Package | 1152-FCBGA (F35, 35x35 mm) | 1152-FCBGA (F35, 35x35 mm) - same | 1152-FCBGA (F35, 35x35 mm) - same | 1152-FCBGA (F35, 35x35 mm) - same | 1152-FCBGA (F35, 35x35 mm) - same | 1152-FCBGA (F35, 35x35 mm) - same |
| Brand | Intel | Intel | Intel | Intel | Intel | Intel |
| Logic Elements | 660,000 | 660,000 | 660,000 | 660,000 | 660,000 | 660,000 |
| HPS Clock Speed | 1.5 GHz | 1.5 GHz | 1.5 GHz | 1.5 GHz | 1.0 GHz (K2 speed grade) | 1.0 GHz (K2 speed grade) |
| Speed Grade | K3 (mid) | K3 | K3 + E2 sub-grade | K3 + E2 sub-grade | K2 (slower) | K2 (slower) |
| Operating Temperature | Industrial -40C to +100C | Commercial 0C to +85C | Industrial -40C to +100C | Commercial 0C to +85C | Industrial -40C to +100C | Commercial 0C to +85C |
| Transceiver Rate | 28.05 Gbps | 28.05 Gbps | 28.05 Gbps | 28.05 Gbps | 28.05 Gbps | 28.05 Gbps |
| Process Node | TSMC 20 nm | TSMC 20 nm | TSMC 20 nm | TSMC 20 nm | TSMC 20 nm | TSMC 20 nm |
Key Differentiators
- Highest-density Arria 10 SX SoC in F35 package with mid-speed K3 grade (vs 10AS066H3F34I2LG)
- Industrial temperature grade with full RoHS/lead-free compliance (vs 10AS066K3F35I2SG)
- F35 1152-FCBGA package optimized for 28 Gbps transceiver signal integrity (vs 10AS066K2F35I2LG (K2 speed grade))
Design Notes
Estimated: Arria 10 SX SoC FPGAs at 660K LE with active transceivers typically dissipate 25-45 W depending on logic utilization, transceiver lane count, and toggle rate. The F35 1152-ball FCBGA exposes a thermal pad requiring an enclosure-top heatsink or board-mounted heat spreader; per Intel Arria 10 thermal guidelines theta_JA is approximately 0.8-1.5 C/W with optimal thermal interface material. Designers must perform application-specific thermal simulation using the Arria 10 PowerPlay early power estimator before committing to PCB stack-up and cooling solution.
The 1152-ball F35 FCBGA requires a high-density PCB stack-up with microvia build-up layers (typically 8-12 layers). Per Intel's Arria 10 pin connection guidelines, route at least 4 PCB layers for the core fabric power rails (0.9V VCC, 1.0V VCCPT), 2-3 layers for transceiver supply filtering, and keep DDR4/3 memory traces length-matched within 25 mils for the HPS hard memory controller. Use 1-oz copper on outer layers and 0.5-oz on inner layers with low-Dk/Df materials for transceiver signal integrity at 28 Gbps.
Common pitfalls when designing with the 10AS066K3F35I2LG include: (1) omitting the HPS reset sequencing - the HPS cold/warm reset pins must follow Intel's recommended sequence with proper POR delay; (2) leaving JTAG chain shared between HPS and FPGA fabric without configuring MSEL pins correctly for the desired boot mode; (3) underestimating power rail sequencing - VCCIO for HPS must ramp before VCC_HPS; (4) using the wrong Quartus Prime device family variant - always select 10AS066K3F35 specifically to ensure pinout correctness in the Fitter.
Per Intel's Arria 10 SX SoC design guidelines, HPS DDR traces must be routed on inner stripline layers with reference planes intact and length-matched within 0.5 ps skew per byte lane. Transceiver channels should follow Intel's recommended pad-out with continuous ground reference beneath the trace and no signal crossovers in adjacent layers. Decoupling capacitor placement must follow the Quartus Prime early pinout-assignment capacitor recommendations: 0402/0201 ceramics within 100 mils of each power pin, bulk capacitors on each rail distributed across the BGA footprint perimeter.
Compliance Information
RoHS compliant per Altera/Intel product page (LG suffix indicates lead-free, RoHS-compliant industrial grade). AEC-Q100 is not applicable for SoC FPGAs. Conflict minerals compliance per Intel's Conflict-Free Smelter Program disclosures.
