10AS066K4F35E3SG - Arria 10 SX SoC FPGA, 660K LE, 1152-FBGA | Intel
MPN: 10AS066K4F35E3SG ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $2850 | $2,850.00 |
| 10 | $2690 | $26,900.00 |
| 100 | $2480 | $248,000.00 |
| 500 | $2295 | $1,147,500.00 |
| 1,000 | $2150 | $2,150,000.00 |
Drop-in alternatives for 10AS066K4F35E3SG — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
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10AS066K4F35E3LG
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$2845.83 / Unit
View Datasheet →10AS066K3F35E3SG
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10AS066K3F35E2SG
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$2950 / Unit
View Datasheet →10AS066K2F35E2SG
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View Datasheet →10AS066K1F35E1HG
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View Datasheet →10AS066K4F35E3SG Maximum Ratings & Electrical Characteristics
| Family | Arria 10 SX SoC FPGA |
| Logic Elements | 660,000 |
| Process Technology | 20 nm |
| Core Voltage | 0.9 V |
| Hard Processor System | Dual ARM Cortex-A9 MPCore with CoreSight |
| Package | 1152-ball FCBGA, 35x35 mm |
| Pin/Ball Count | 1152 |
| Operating Temperature Grade | Industrial / extended (per ordering code E3) |
| RAM Size (HPS) | 256 KB |
| Peripherals | DMA, POR, WDT |
| Connectivity | EBI/EMI, Ethernet, I2C, MMC/SD/SDIO, SPI, UART |
| Architecture | MCU + FPGA |
| Mounting Type | Surface Mount (BGA) |
| RoHS Status | Compliant |
| Lifecycle Status | Active |
10AS066K4F35E3SG 1152-ball fcbga, 35x35 mm Pin Configuration Guide
Complete pinout information for 10AS066K4F35E3SG (1152-ball fcbga, 35x35 mm package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for 10AS066K4F35E3SG.
Refer to the datasheet for full pin configuration.
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
10AS066K4F35E3SG is suitable for 6 applications: Industrial Motor Control, Software Defined Radio (SDR), Medical Imaging Preprocessing, Test and Measurement Instrumentation, Broadcast Video Processing, Aerospace and Defense Signal Processing.
Industrial Motor Control
The 10AS066K4F35E3SG's dual-core ARM Cortex-A9 MPCore hard processor system runs real-time control loops (FOC, sensorless control) at deterministic latency, while the 660K-logic-element FPGA fabric handles high-speed PWM generation, encoder decoding, and safety logic in parallel. The HPS connectivity peripherals (EBI/EMI, SPI for ADC/DAC, UART for HMI) reduce external component count. Industrial motor drives with 100 kHz+ control loops benefit from the FPGA's deterministic nanosecond response alongside Linux/RTOS capability on the HPS.
Recommended
Software Defined Radio (SDR)
The Arria 10 SX 660K-logic-element FPGA fabric in the 10AS066K4F35E3SG is well-suited to wideband SDR baseband processing, including FFT/iFFT pipelines, channelization, and digital up/down conversion. Multi-gigabit transceivers handle ADC/DAC interface to RF front ends. The HPS runs waveform scheduling, network stacks, and management plane software under Linux. SDR platforms targeting 4G/5G small cells, tactical radio, or test & measurement benefit from this SoC partitioning, with FPGA doing DSP and the ARM cores doing protocol and housekeeping.
Recommended
Medical Imaging Preprocessing
Medical imaging systems (ultrasound, endoscopy, CT preprocessing) require real-time pixel pipelines that the 10AS066K4F35E3SG's 660K-logic-element FPGA fabric accelerates at line rate. The HPS runs the user interface, patient database I/O, and image post-processing under a Linux stack. DMA engines in the HPS move preprocessed frames directly to DDR for efficient memory bandwidth. Low-latency FPGA response is essential for transducer beamforming and Doppler processing where millisecond-level delay matters clinically.
Recommended
Test and Measurement Instrumentation
Test equipment - oscilloscopes, protocol analyzers, BERT systems - leverage the 10AS066K4F35E3SG's high-speed transceivers and parallel FPGA fabric to capture and analyze multi-gigabit signals. The dual-core Cortex-A9 HPS runs the instrument UI, SCPI command parsing, and LXI network stack. Memory bandwidth between FPGA and HPS through AXI bridges is critical for waveform streaming to DDR. The 1152-ball FCBGA provides the signal escape required for high-channel-count instruments.
Recommended
Broadcast Video Processing
The 10AS066K4F35E3SG handles broadcast-grade video processing - format conversion, scaling, chroma keying, and overlay - in its FPGA fabric at full frame rate (60 fps 4K). The HPS manages file I/O, network streaming, and codec control via SPI/UART peripherals. SDI interfaces through transceivers connect directly to the FPGA fabric. Live production switchers and contribution encoders benefit from deterministic FPGA latency combined with Linux network stacks for IP-based workflows like SMPTE ST 2110.
Recommended
Aerospace and Defense Signal Processing
Avionics and defense applications - radar preprocessing, electronic warfare, secure communications - leverage the 10AS066K4F35E3SG's combination of FPGA DSP throughput and HPS-based crypto/mission software. The 1152-ball FCBGA package supports ruggedized PCB stack-ups required for vibration and thermal environments. Industrial/extended operating temperature grades (E3, I3) available in the same F35 footprint allow design reuse across commercial and rugged variants. HPS runs RTOS for deterministic mission timing while FPGA handles high-bandwidth sensor data.
Recommended
Recommended Products Summary
Engineering reference data for 10AS066K4F35E3SG — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | 10AS066K4F35E3LG | 10AS066K3F35E3SG | 10AS066K3F35E2SG | 10AS066K2F35E2SG | 10AS066K1F35E1HG |
|---|---|---|---|---|---|---|
| Brand | Intel | Intel | Intel | Intel | Intel | Intel |
| Package | 1152-FCBGA (35x35 mm) | 1152-FCBGA (35x35 mm) - same | 1152-FCBGA (35x35 mm) - same | 1152-FCBGA (35x35 mm) - same | 1152-FCBGA (35x35 mm) - same | 1152-FCBGA (35x35 mm) - same |
| Logic Elements | 660,000 | 660,000 | 660,000 | 660,000 | 660,000 | 660,000 |
| Device Code Tier | K4 (highest) | K4 | K3 | K3 | K2 | K1 (lowest) |
| Temperature/Speed Grade | E3 | E3 | E3 | E2 | E2 | E1 |
| Hard Processor System | Dual ARM Cortex-A9 | Dual ARM Cortex-A9 | Dual ARM Cortex-A9 | Dual ARM Cortex-A9 | Dual ARM Cortex-A9 | Dual ARM Cortex-A9 |
| Process Technology | 20 nm | 20 nm | 20 nm | 20 nm | 20 nm | 20 nm |
| Approx. Unit Price (qty 1, USD) | 2,850 | 2,850 | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] |
Key Differentiators
- Highest-tier device code (K4) within the 660K-LE Arria 10 SX family (vs 10AS066K3F35E3SG)
- Hard ARM Cortex-A9 MPCore integrated on-die (vs Non-SoC Arria 10 GX/GX variants)
- 20 nm process with transceiver performance (vs Cyclone V SoC (older 28 nm process))
- 1152-ball F35 FCBGA provides highest I/O escape (vs F34 package variants (10AS066H4F34E3SG))
Design Notes
The 1152-ball FCBGA F35 package requires a high-density PCB stack-up with microvias. Use 1 oz copper outer layers, 0.5 oz inner layers, and an ENIG or OSP surface finish. Decoupling must follow the Intel Arria 10 pin connection guidelines; place bulk capacitors within 100 mil of the balls, and high-frequency 0.1 uF/0.01 uF capacitors directly under the package BGA escape pattern. Estimate: ~200 decoupling capacitors are typical for Arria 10 SX designs.
Estimated: at maximum utilization (high toggle rate, full transceiver activity, HPS at full load), the 10AS066K4F35E3SG dissipates approximately 20-25 W. The 35x35 mm FCBGA junction-to-ambient thermal resistance with adequate thermal vias and a heat spreader is typically 1-2 C/W. A heat sink or forced-air cooling is required for industrial ambient operation; passive cooling alone is insufficient at full power. Plan thermals early in the PCB layout phase.
Arria 10 SX requires multiple power rails - core VCC (0.9 V), HPS VCC (separate sequencing), transceiver rails (VCCR/VCCP/VCCPT), and I/O banks. Power sequencing must follow the Intel Arria 10 power management guidelines to avoid latch-up. Use a dedicated power management IC such as the Intel Enpirion EM11K or similar with sequenced enable outputs. The HPS rail must be stable before the FPGA core rail to ensure deterministic boot.
Transceiver channels (up to 24 in K4 tier) require matched-length routing with controlled impedance (typically 85-100 ohm differential). Keep AC-coupling capacitors within 200 mil of the transceiver ball pads. Reference the Intel Arria 10 SX transceiver layout guidelines for via pattern and ground stitching. Length matching within an xAUI or PCIe interface must be within 5 mil for reliable operation.
Common pitfalls with Arria 10 SX SoC FPGAs: (1) failing to configure the HPS boot source pins correctly for QSPI/NAND/NOR; (2) not providing enough decoupling for simultaneous FPGA and HPS transients; (3) using incorrect Quartus Prime device selection (K3 vs K4 K1 designations affect transceiver IP); (4) violating the HPS-to-FPGA AXI bridge bandwidth limits when moving large DMA blocks; (5) bypassing the FPGA configuration CRC check leading to silent failures.
Compliance Information
RoHS compliant per Intel product page. Halogen-free status not explicitly stated in provided data; set to 'unknown' per data authenticity rules. AEC-Q100 not applicable - this is a complex SoC FPGA, not an automotive-grade simple IC.
