10AS066K3F35I2SG - Arria 10 SX 660K LE SoC FPGA | Altera
MPN: 10AS066K3F35I2SG ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $3938.2 | $3,938.20 |
| 5 | $3790 | $18,950.00 |
| 10 | $3650 | $36,500.00 |
| 25 | $3520 | $88,000.00 |
| 50 | $3405 | $170,250.00 |
Drop-in alternatives for 10AS066K3F35I2SG — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
10AS066K3F35I2LG
✅ Drop-In ⚠️ 参数待验证✓ In Stock
$3712.06 / Unit
View Datasheet →10AS066K3F35E2SG
✅ Drop-In ⚠️ 参数待验证✓ In Stock
$2950 / Unit
View Datasheet →10AS066K2F35I2SG
✅ Drop-In ⚠️ 参数待验证✓ In Stock
$5750 / Unit
View Datasheet →10AS066K2F35I2LG
✅ Drop-In ⚠️ 参数待验证✓ In Stock
$5650.15 / Unit
View Datasheet →10AS066H3F34I2SG
✅ Drop-In ⚠️ 参数待验证✓ In Stock
$3200 / Unit
View Datasheet →10AS057K4F35I3SG
✅ Drop-In ⚠️ 参数待验证✓ In Stock
$2185 / Unit
View Datasheet →10AS066K3F35I2SG Maximum Ratings & Electrical Characteristics
| Family | Arria 10 SX |
| Device Family | Arria 10 SX SoC FPGA |
| Logic Elements | 660K |
| Hard Processor System | Dual ARM Cortex-A9 MPCore with CoreSight |
| Core Speed Grade | 1.5 GHz |
| Package | 1152-FBGA, FC (35x35 mm) |
| Package Type | Flip-chip BGA |
| I/O Count | 396 user I/O |
| Operating Temperature | -40C to +100C (Industrial) |
| Speed Grade | -3 |
| Process Technology | 20 nm |
| Transceivers | Multi-gigabit transceivers (up to 28.05 Gbps) |
| External Memory Support | DDR4 up to 2400 Mbps via HPS; DDR3/DDR4/LPDDR3 via FPGA fabric |
| Mounting Type | Surface Mount |
| RoHS Status | Compliant |
10AS066K3F35I2SG flip-chip bga Pin Configuration Guide
Complete pinout information for 10AS066K3F35I2SG (flip-chip bga package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for 10AS066K3F35I2SG.
Refer to the datasheet for full pin configuration.
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
10AS066K3F35I2SG is suitable for 8 applications: 4K/UHD Video Processing, Wireless Baseband & Radio Aggregation, Radar Signal Processing, Industrial Machine Vision, High-Speed Data Acquisition, Broadcast Video Encoding & Transcoding, Aerospace & Defense Secure Processing, Medical Imaging & Diagnostic Systems.
4K/UHD Video Processing
The 10AS066K3F35I2SG's 660K logic elements and variable-precision DSP blocks deliver the throughput required for real-time 4K/UHD video pipelines at 60 fps, where pixel rates can exceed 500 Mpixels per second. The device's speed grade -3 supports the Fmax needed for multi-channel deinterlacing, scaling, and motion-adaptive noise reduction. The dual ARM Cortex-A9 HPS handles protocol stacks such as RTP/RTSP, HDMI-CEC, and HDCP control-plane tasks while the FPGA fabric accelerates compute-heavy kernels including color-space conversion (4:4:4 to 4:2:0) and high-dynamic-range tone mapping. The 1152-FBGA F35 package provides the I/O density to support HDMI 2.0, DisplayPort 1.4, and 12G-SDI interfaces side by side without external bridge chips.
Recommended
Wireless Baseband & Radio Aggregation
In wireless baseband and small-cell aggregation designs, the 10AS066K3F35I2SG pairs multi-gigabit transceivers with DSP-heavy fabric for CPRI/OBSAI fronthaul aggregation and channel-card processing. The speed grade -3 enables 28.05 Gbps transceiver operation, supporting 4G/5G fronthaul at full CPRI line rates while the dual ARM Cortex-A9 HPS runs PHY/control software. Designers benefit from hardened PCIe Gen3 and DDR4 controllers in the HPS subsystem for backhaul connectivity, plus 660K logic elements to implement digital predistortion, crest-factor reduction, and crest-factor enhancement algorithms.
Recommended
Radar Signal Processing
Radar front-end systems for ground, marine, and weather applications use the 10AS066K3F35I2SG to digitize and process wide-bandwidth intermediate-frequency signals with deterministic latency. The 660K logic elements and DSP blocks implement multi-pulse Doppler processing, CFAR detection, and beamforming at thousands of updates per second. The dual ARM Cortex-A9 HPS runs track-management software, plot extraction, and the radar display stack. Speed grade -3 ensures the Fmax headroom required for high-resolution SAR imaging modes where clock rates exceed 400 MHz on FPGA datapaths.
Recommended
Industrial Machine Vision
The 10AS066K3F35I2SG integrates Camera Link, CoaXPress, and GigE Vision image acquisition alongside image-processing pipelines in a single SoC, replacing discrete frame-grabber plus industrial PC implementations. The 396 user I/O provide ample GPIO and high-speed serial lanes for multiple simultaneous cameras; the FPGA fabric accelerates defect detection, template matching, and convolutional neural network inference at line rates. The dual ARM Cortex-A9 HPS runs the vision control software, PLC integration, and OPC-UA reporting - all without an external processor. Industrial temperature rating ensures operation on factory floors from -40C to +100C.
Recommended
High-Speed Data Acquisition
Test-and-measurement, medical imaging, and scientific instrumentation rely on the 10AS066K3F35I2SG to capture, buffer, and stream multiple gigabytes per second of ADC data into host CPUs or storage. The 660K logic elements implement packet formation, channel skew correction, and lossy compression; the HPS manages DMA transfers to DDR4 at up to 2400 Mbps. Speed grade -3 supports ADC sampling rates above 1 GSPS where FPGAs are typically underclocked relative to ADC output rates. The 1152-ball FCBGA exposes the I/O density required for parallel LVDS and JESD204B/C interfaces.
Recommended
Broadcast Video Encoding & Transcoding
Broadcast encoders and transcoders for HEVC/H.265 and AV1 codecs leverage the 10AS066K3F35I2SG's DSP-heavy fabric and 660K logic elements to accelerate motion estimation, intra-prediction, and transform coding at multi-channel 4K rates. The dual ARM Cortex-A9 HPS manages IP transport, RTP packetization, and PSIP/SI metadata, while PCIe Gen3 hard IP enables direct attachment to host servers for contribution feeds. The 1152-ball FCBGA package supports multiple 12G-SDI inputs, 25G Ethernet aggregation, and HDMI 2.1 outputs in a single SoC without external bridge silicon.
Recommended
Aerospace & Defense Secure Processing
Avionics, mission computers, and secure communications equipment use the 10AS066K3F35I2SG's dual ARM Cortex-A9 HPS for vetted RTOS execution while the FPGA fabric accelerates cryptographic primitives, signal processing, and image fusion. The 20 nm process node and -40C to +100C industrial temperature range suit ruggedized environments; the F35 package provides high I/O density for MIL-STD-1553, ARINC 429, and SpaceWire interfaces through soft IP cores. Speed grade -3 ensures deterministic timing margins for safety-critical DO-254 design assurance levels.
Recommended
Medical Imaging & Diagnostic Systems
Ultrasound, MRI, and CT imaging systems use the 10AS066K3F35I2SG for parallel beamforming across hundreds of channels with deterministic microsecond latency. The 660K logic elements implement matched filters, harmonic imaging, and elastography at frame rates exceeding 60 fps; the HPS subsystem handles DICOM packaging, patient-data interfaces, and secure boot. Speed grade -3 supports the Fmax required for high-frequency transducers, while the DDR4 hard controller in the HPS subsystem streams reconstructed images to the host display with zero-copy DMA transfers.
Recommended
Recommended Products Summary
Engineering reference data for 10AS066K3F35I2SG — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | 10AS066K3F35I2LG | 10AS066K3F35E2SG | 10AS066K2F35I2SG | 10AS066K2F35I2LG | 10AS066H3F34I2SG | 10AS057K4F35I3SG |
|---|---|---|---|---|---|---|---|
| Brand | Altera | Altera | Altera | Altera | Altera | Altera | Altera |
| Package | 1152-FBGA, FC (35x35) | 1152-FBGA, FC (35x35) - same | 1152-FBGA, FC (35x35) - same | 1152-FBGA, FC (35x35) - same | 1152-FBGA, FC (35x35) - same | 1152-FBGA, FC (34x34) - different outline | 1152-FBGA, FC (35x35) - same |
| Logic Elements | 660K | 660K - same | 660K - same | 660K - same | 660K - same | 660K - same | 570K (-13%) |
| Speed Grade | -3 | -3 - same | -3 - same | -2 (-15% Fmax) | -2 (-15% Fmax) | -3 - same | -4 (faster than -3) |
| Temperature Grade | Industrial (-40C to +100C) | Industrial - same | Extended (E2) | Industrial - same | Industrial - same | Industrial - same | Industrial - same |
| Hard Processor System | Dual ARM Cortex-A9 | Dual ARM Cortex-A9 - same | Dual ARM Cortex-A9 - same | Dual ARM Cortex-A9 - same | Dual ARM Cortex-A9 - same | Dual ARM Cortex-A9 - same | Dual ARM Cortex-A9 - same |
| User I/O | 396 | 396 - same | 396 - same | 396 - same | 396 - same | 396 (F34 footprint variant) | 396 - same |
| Process Technology | 20 nm | 20 nm - same | 20 nm - same | 20 nm - same | 20 nm - same | 20 nm - same | 20 nm - same |
| Approx. Unit Price (USD, qty 1) | $3,938.20 | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] |
Key Differentiators
- Highest speed grade in the F35 footprint at 660K logic elements (vs 10AS066K2F35I2SG)
- Largest fabric in the F35 package (vs 10AS057K4F35I3SG)
- Industrial temperature grade by default (vs 10AS066K3F35E2SG)
- Same-package drop-in within the Arria 10 SX family (vs 10AS066H3F34I2SG)
Design Notes
The 1152-ball F35 flip-chip BGA has a fine ball pitch requiring escape routing on inner high-density-interconnect layers. Use a 12-layer or 14-layer stack-up with 0.4 mm pitch escape and microvia-in-pad construction for the inner rows of the BGA. Place decoupling capacitors on the top layer directly under the BGA shadow using 0.1 uF ceramic X7R in 0201 or 0402 size to minimize inductance.
Estimated: at typical 4K video processing utilization, the 10AS066K3F35I2SG dissipates between 8 W and 15 W. Use a high-performance thermal interface material (TIM) with conductivity above 3 W/mK and a heat sink with finned profile. The 35 mm x 35 mm package outline provides adequate surface area for a heat spreader; forced-air cooling at 200 LFM is required when ambient exceeds 60C.
Decouple the core supply with bulk tantalum or polymer capacitors (220 uF to 470 uF) plus high-frequency ceramic (10 uF and 0.1 uF) close to the package. The Arria 10 SX requires multiple voltage rails (VCC, VCCPT, VCCPGM, VCCA_PLL, VCCH_GXB) with specific sequencing; follow the Altera PowerPlay and Pin Connection Guidelines for power-on-reset behavior and hot-socketing requirements.
The multi-gigabit transceivers support up to 28.05 Gbps operation; route these as 100 ohm differential pairs with controlled-impedance stack-up (typically stripline on inner layers). Use AC-coupled capacitors at transmitter outputs and DC-coupling on receiver inputs per the device datasheet. Place reference plane cuts and via patterns to minimize crosstalk between adjacent channels.
Do not assume the HPS subsystem boots independently of FPGA configuration - the Arria 10 SX boots the HPS first then releases FPGA fabric reset, so design your system software to handle HPS-as-master boot ordering. Also note that the K3 speed grade designation uses a different ordering code structure than older Altera FPGAs; verify the ordering part number matches the device pin-out file before committing to PCB layout.
Compliance Information
RoHS compliance confirmed via Altera/Intel product page. AEC-Q100 not applicable (industrial FPGA, not automotive-grade). REACH, halogen-free, and conflict-minerals status not explicitly stated in provided data - recommend verifying with Intel product compliance documents.
