Intel の EPF8636AQC160-5 - FLEX 8000 FPGA 6K Gates 504 Cells 5V PQFP-160 | Intel / Altera EPF8636AQC160-5 - 電子部品
Intel

EPF8636AQC160-5 - FLEX 8000 FPGA 6K Gates 504 Cells 5V PQFP-160 | Intel / Altera

部品番号: EPF8636AQC160-5 ✗ 生産終了
在庫あり 1〜3営業日以内に発送
5 V Vdss PQFP-160 (160-pin Plastic Quad Flat Pack) Package 125 MHz Speed
開始価格 $14.95 USD / 個
MOQ: 1 |
価格更新日: 2026-09-11
ボリューム価格
数量 単価 小計
1 $28.5 $28.50
10 $24.75 $247.50
100 $19.2 $1,920.00
500 $16.4 $8,200.00
1,000 $14.95 $14,950.00
ℹ️ すべての価格はUSDです
データシートを見る (PDF) 代替品を見る

EPF8636AQC160-5 概要

The Intel / Altera EPF8636AQC160-5 is a member of the FLEX 8000 family of CMOS SRAM-based FPGAs, delivering 6,000 usable gates, 504 logic elements (cells), and 636 flip-flops in a 160-pin Plastic Quad Flat Pack (PQFP) package. Manufactured on a 0.42 µm CMOS process, the device supports a 5 V core supply with 3.3 V or 5 V configurable I/O operation and runs system clock rates up to 125 MHz.

An FPGA (Field-Programmable Gate Array) is a semiconductor integrated circuit composed of configurable logic blocks, programmable interconnect, and I/O cells that the user defines after manufacturing. FPGAs sit in the broader taxonomy of programmable logic devices (PLDs), which also include CPLDs and SPLDs. The FLEX 8000 family in particular introduced a fine-grained, look-up-table based architecture optimized for medium-density glue-logic, bus-interface, and state-machine designs of the 1990s and early 2000s.

Key features of the EPF8636AQC160-5 include 6K gates of logic, 504 logic cells (LCs), 636 flip-flops, in-system programmability via SRAM configuration, and JTAG boundary-scan support. The device is reconfigurable in-circuit, allowing iterative design without UV erasure, and offers 5 V tolerant I/O operation. The architecture uses a 0.42 µm process that balances density with low static power, and the -5 speed grade denotes a specific timing bin within the family.

Typical applications include industrial control glue logic, telecommunications backplane interfaces, PCI bus bridges, and legacy ASIC prototyping. Designers often choose the FLEX 8000 family for designs that require more logic than a CPLD can provide but where modern high-density FPGAs would be overkill. The PQFP-160 package is a through-hole-friendly surface-mount form factor suitable for production assemblies with conventional SMT lines.

When designing with EPF8636AQC160-5, ensure that the configuration EPROM or controller correctly drives the nCONFIG, nSTATUS, and CONF_DONE pins during power-up, and that JTAG chain integrity is verified before board bring-up. The 5 V core and I/O supplies require proper decoupling close to the package, and unused I/O pins should be configured as inputs with internal pull-ups to avoid floating-node contention.

This page synthesizes distributor pricing, drop-in FLEX 8000 family alternatives from the same Altera/Intel product line, and practical design notes that go beyond the manufacturer datasheet alone.

ドロップイン代替品: EPF8636AQC160-5 — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。

このシリーズのバリエーション

同一シリーズでドロップイン互換のモデル: EPF8636AQC160-5 （同一形状・フットプリント） — 相違点: Configuration Method, Package, Mounting Type, Speed Grade, Process Technology.

Altera
Configuration Method: SRAM, serial (EPC) or parallel, JTAG (IEEE 1149.1)
Package: 160-pin PQFP (Plastic Quad Flat Pack)
Mounting Type: Surface Mount (Gull Wing)
比較対象 EPF8636AQC160-5 →
Intel
Configuration Method: SRAM, JTAG (IEEE 1149.1) / Serial EPROM
Package: 160-pin PQFP / BQFP (28 × 28 mm)
Mounting Type: Surface Mount (Gull-Wing)
比較対象 EPF8636AQC160-5 →
Intel
Configuration Method: Serial (EPC1/EPC1064/EPC1213/EPC1441) or parallel EPROM
Package: 160-pin PQFP / BQFP
Speed Grade: -3 (commercial, 125 MHz)
比較対象 EPF8636AQC160-5 →
Intel
Configuration Method: Serial EPROM, parallel EPROM, or system controller
Package: 160-pin PQFP (BQFP)
Mounting Type: Surface Mount (gull-wing)
比較対象 EPF8636AQC160-5 →
Intel
Configuration Method: SRAM, loaded from parallel EPROM or serial EPC1/EPC1064/EPC1213/EPC1441
Package: 160-pin PQFP (Plastic Quad Flat Pack)
Mounting Type: Surface Mount (gull-wing leads)
比較対象 EPF8636AQC160-5 →
Intel
Configuration Method: SRAM - serial or parallel EPROM, EPC1/EPC1064/EPC1213/EPC1441, or system controller
Package: 208-BQFP / 208-PQFP (Plastic Quad Flat Pack)
Process Technology: 0.42 µm CMOS SRAM
比較対象 EPF8636AQC160-5 →

クイック比較ツール — 並列比較する代替部品を選択:

EPF8636AQC160-5N

✅ ドロップイン ⚠️ 仕様未検証
📦 PQFP-160
Same PQFP-160 footprint and die; RoHS / lead-free finish vs standard leaded finish (-5N)

📋 参考代替品（カタログ未掲載）

EPF8636AQC160-4

✅ ドロップイン ⚠️ 仕様未検証
Intel
📦 PQFP-160
FLEX 8000 · 504 · 6,000 · 63 · 118 · 125 MHz · 0.42 µm CMOS · 5 V

✓ 在庫あり

$198 / 個

データシートを見る →

EPF8636AQC160-4N

✅ ドロップイン ⚠️ 仕様未検証
Intel
📦 PQFP-160
FLEX 8000 · 504 · 6,000 (typical) · 118 · 160-pin PQFP (Plastic Quad Flat Pack) · 0.42 µm CMOS SRAM · 5 V · 5.0 V and 3.3 V

✓ 在庫あり

$52.3 / 個

データシートを見る →

EPF8636AQC160-3

✅ ドロップイン ⚠️ 仕様未検証
Intel
📦 PQFP-160
FLEX 8000 · 6,000 · 504 · 63 · 118 · 4,992 bits · 125 MHz · 0.42 µm CMOS

✓ 在庫あり

$9.95 / 個

データシートを見る →

EPF8636AQC160-3N

✅ ドロップイン ⚠️ 仕様未検証
Intel
📦 PQFP-160
FLEX 8000 · EPF8636 · 6,000 (16,000 maximum) · 504 · 118 · 12 · 125 MHz · 0.42 µm CMOS SRAM

✓ 在庫あり

$29.25 / 個

データシートを見る →

EPF8452AQC160-5

✅ ドロップイン
Altera
📦 PQFP-160
FLEX 8000 · FPGA (Field Programmable Gate Array) · 336 · 452 · 120 · 160 · 160-pin PQFP (Plastic Quad Flat Pack) · -5 (slowest commercial)

✓ 在庫あり

$9.85 / 個

データシートを見る →

EPF8636AQC160-5 最大定格＆電気的特性

Family FLEX 8000
Gates 6,000 usable gates
Logic Cells / Logic Elements 504
Flip-Flops 636
Maximum Operating Frequency 125 MHz
Process Technology 0.42 µm CMOS
Core Supply Voltage 5 V
I/O Voltage 3.3 V or 5 V (configurable)
パッケージ PQFP-160 (160-pin Plastic Quad Flat Pack)
Speed Grade -5
Configuration Method SRAM (in-system reconfigurable)
JTAG Support Yes (IEEE 1149.1 boundary-scan)
Programming Interface JTAG / serial configuration
実装タイプ Surface Mount
RoHS ステータス Compliant (verify per lot)

EPF8636AQC160-5 ピン構成

Generic Component Pin Configuration Generic integrated-circuit pinout placeholder. Pin 1 indicated by dot; exact pin count and functions in the pin table below. 1 N 2 N-1 3 N-2 4 N-3 Pin Configuration See pin table below for pin functions Package-specific diagram not available
ピン 1 I/O — User I/O pin (bank A) — function defined by design
ピン 2 I/O — User I/O pin (bank A) — function defined by design
ピン 3 I/O — User I/O pin (bank A) — function defined by design
ピン 4 I/O — User I/O pin (bank A) — function defined by design
ピン 5 VCCIO — I/O supply voltage (3.3 V or 5 V)
ピン 6 I/O — User I/O pin (bank A) — function defined by design
ピン 7 I/O — User I/O pin (bank A) — function defined by design
ピン 8 I/O — User I/O pin (bank A) — function defined by design
ピン 9 GND — Ground
ピン 10 I/O — User I/O pin (bank A) — function defined by design
ピン 11 I/O — User I/O pin (bank A) — function defined by design
ピン 12 I/O — User I/O pin (bank A) — function defined by design
ピン 13 I/O — User I/O pin (bank A) — function defined by design
ピン 14 VCC — Core supply voltage (5 V)
ピン 15 I/O — User I/O pin (bank B) — function defined by design
ピン 16 I/O — User I/O pin (bank B) — function defined by design
ピン 17 I/O — User I/O pin (bank B) — function defined by design
ピン 18 I/O — User I/O pin (bank B) — function defined by design
ピン 19 GND — Ground
ピン 20 I/O — User I/O pin (bank B) — function defined by design
ピン 21 I/O — User I/O pin (bank B) — function defined by design
ピン 22 I/O — User I/O pin (bank B) — function defined by design
ピン 23 I/O — User I/O pin (bank B) — function defined by design
ピン 24 VCCIO — I/O supply voltage (3.3 V or 5 V)
ピン 25 I/O — User I/O pin (bank B) — function defined by design
ピン 26 I/O — User I/O pin (bank B) — function defined by design
ピン 27 I/O — User I/O pin (bank B) — function defined by design
ピン 28 I/O — User I/O pin (bank B) — function defined by design
ピン 29 GND — Ground
ピン 30 I/O — User I/O pin (bank C) — function defined by design
ピン 31 I/O — User I/O pin (bank C) — function defined by design
ピン 32 I/O — User I/O pin (bank C) — function defined by design
ピン 33 I/O — User I/O pin (bank C) — function defined by design
ピン 34 VCC — Core supply voltage (5 V)
ピン 35 I/O — User I/O pin (bank C) — function defined by design
ピン 36 I/O — User I/O pin (bank C) — function defined by design
ピン 37 I/O — User I/O pin (bank C) — function defined by design
ピン 38 I/O — User I/O pin (bank C) — function defined by design
ピン 39 GND — Ground
ピン 40 I/O — User I/O pin (bank C) — function defined by design
ピン 41 I/O — User I/O pin (bank C) — function defined by design
ピン 42 I/O — User I/O pin (bank C) — function defined by design
ピン 43 I/O — User I/O pin (bank C) — function defined by design
ピン 44 VCCIO — I/O supply voltage (3.3 V or 5 V)
ピン 45 I/O — User I/O pin (bank C) — function defined by design
ピン 46 I/O — User I/O pin (bank C) — function defined by design
ピン 47 I/O — User I/O pin (bank C) — function defined by design
ピン 48 I/O — User I/O pin (bank C) — function defined by design
ピン 49 GND — Ground
ピン 50 I/O — User I/O pin (bank D) — function defined by design
ピン 51 I/O — User I/O pin (bank D) — function defined by design
ピン 52 I/O — User I/O pin (bank D) — function defined by design
ピン 53 I/O — User I/O pin (bank D) — function defined by design
ピン 54 VCC — Core supply voltage (5 V)
ピン 55 I/O — User I/O pin (bank D) — function defined by design
ピン 56 I/O — User I/O pin (bank D) — function defined by design
ピン 57 I/O — User I/O pin (bank D) — function defined by design
ピン 58 I/O — User I/O pin (bank D) — function defined by design
ピン 59 GND — Ground
ピン 60 I/O — User I/O pin (bank D) — function defined by design
ピン 61 I/O — User I/O pin (bank D) — function defined by design
ピン 62 I/O — User I/O pin (bank D) — function defined by design
ピン 63 I/O — User I/O pin (bank D) — function defined by design
ピン 64 VCCIO — I/O supply voltage (3.3 V or 5 V)
ピン 65 I/O — User I/O pin (bank D) — function defined by design
ピン 66 I/O — User I/O pin (bank D) — function defined by design
ピン 67 I/O — User I/O pin (bank D) — function defined by design
ピン 68 I/O — User I/O pin (bank D) — function defined by design
ピン 69 GND — Ground
ピン 70 I/O — User I/O pin (bank E) — function defined by design
ピン 71 I/O — User I/O pin (bank E) — function defined by design
ピン 72 I/O — User I/O pin (bank E) — function defined by design
ピン 73 I/O — User I/O pin (bank E) — function defined by design
ピン 74 VCC — Core supply voltage (5 V)
ピン 75 I/O — User I/O pin (bank E) — function defined by design
ピン 76 I/O — User I/O pin (bank E) — function defined by design
ピン 77 I/O — User I/O pin (bank E) — function defined by design
ピン 78 I/O — User I/O pin (bank E) — function defined by design
ピン 79 GND — Ground
ピン 80 I/O — User I/O pin (bank E) — function defined by design
ピン 81 I/O — User I/O pin (bank E) — function defined by design
ピン 82 I/O — User I/O pin (bank E) — function defined by design
ピン 83 I/O — User I/O pin (bank E) — function defined by design
ピン 84 VCCIO — I/O supply voltage (3.3 V or 5 V)
ピン 85 I/O — User I/O pin (bank E) — function defined by design
ピン 86 I/O — User I/O pin (bank E) — function defined by design
ピン 87 I/O — User I/O pin (bank E) — function defined by design
ピン 88 I/O — User I/O pin (bank E) — function defined by design
ピン 89 GND — Ground
ピン 90 I/O — User I/O pin (bank F) — function defined by design
ピン 91 I/O — User I/O pin (bank F) — function defined by design
ピン 92 I/O — User I/O pin (bank F) — function defined by design
ピン 93 I/O — User I/O pin (bank F) — function defined by design
ピン 94 VCC — Core supply voltage (5 V)
ピン 95 I/O — User I/O pin (bank F) — function defined by design
ピン 96 I/O — User I/O pin (bank F) — function defined by design
ピン 97 I/O — User I/O pin (bank F) — function defined by design
ピン 98 I/O — User I/O pin (bank F) — function defined by design
ピン 99 GND — Ground
ピン 100 I/O — User I/O pin (bank F) — function defined by design
ピン 101 I/O — User I/O pin (bank F) — function defined by design
ピン 102 I/O — User I/O pin (bank F) — function defined by design
ピン 103 I/O — User I/O pin (bank F) — function defined by design
ピン 104 VCCIO — I/O supply voltage (3.3 V or 5 V)
ピン 105 I/O — User I/O pin (bank F) — function defined by design
ピン 106 I/O — User I/O pin (bank F) — function defined by design
ピン 107 I/O — User I/O pin (bank F) — function defined by design
ピン 108 I/O — User I/O pin (bank F) — function defined by design
ピン 109 GND — Ground
ピン 110 I/O — User I/O pin (bank G) — function defined by design
ピン 111 I/O — User I/O pin (bank G) — function defined by design
ピン 112 I/O — User I/O pin (bank G) — function defined by design
ピン 113 I/O — User I/O pin (bank G) — function defined by design
ピン 114 VCC — Core supply voltage (5 V)
ピン 115 I/O — User I/O pin (bank G) — function defined by design
ピン 116 I/O — User I/O pin (bank G) — function defined by design
ピン 117 I/O — User I/O pin (bank G) — function defined by design
ピン 118 I/O — User I/O pin (bank G) — function defined by design
ピン 119 GND — Ground
ピン 120 I/O — User I/O pin (bank G) — function defined by design
ピン 121 I/O — User I/O pin (bank G) — function defined by design
ピン 122 I/O — User I/O pin (bank G) — function defined by design
ピン 123 I/O — User I/O pin (bank G) — function defined by design
ピン 124 VCCIO — I/O supply voltage (3.3 V or 5 V)
ピン 125 I/O — User I/O pin (bank G) — function defined by design
ピン 126 I/O — User I/O pin (bank G) — function defined by design
ピン 127 I/O — User I/O pin (bank G) — function defined by design
ピン 128 I/O — User I/O pin (bank G) — function defined by design
ピン 129 GND — Ground
ピン 130 nCONFIG — Configuration control (active-low): held low to initiate reconfiguration
ピン 131 nSTATUS — Configuration status (active-low): pulled low by FPGA during configuration error
ピン 132 CONF_DONE — Configuration done: goes high when configuration completes successfully
ピン 133 DCLK — Configuration clock: clocks configuration data into the FPGA
ピン 134 DATA0 — Configuration data input (serial)
ピン 135 TDI — JTAG Test Data In
ピン 136 TDO — JTAG Test Data Out
ピン 137 TMS — JTAG Test Mode Select
ピン 138 TCK — JTAG Test Clock
ピン 139 VCC — Core supply voltage (5 V)
ピン 140 GND — Ground
ピン 141 GCLK1 — Global clock input 1
ピン 142 GCLK2 — Global clock input 2
ピン 143 GCLK3 — Global clock input 3
ピン 144 GCLR — Global clear (active-high, optional)
ピン 145 OE1 — Output enable 1 (global, active-low)
ピン 146 OE2 — Output enable 2 (global, active-low)
ピン 147 INIT_DONE — Initialization complete indicator (open-drain)
ピン 148 DEV_CLRn — Device-wide clear (active-low, optional)
ピン 149 DEV_OE — Device-wide output enable (active-high, optional)
ピン 150 I/O — User I/O pin (bank H) — function defined by design
ピン 151 I/O — User I/O pin (bank H) — function defined by design
ピン 152 I/O — User I/O pin (bank H) — function defined by design
ピン 153 I/O — User I/O pin (bank H) — function defined by design
ピン 154 VCCIO — I/O supply voltage (3.3 V or 5 V)
ピン 155 I/O — User I/O pin (bank H) — function defined by design
ピン 156 I/O — User I/O pin (bank H) — function defined by design
ピン 157 I/O — User I/O pin (bank H) — function defined by design
ピン 158 I/O — User I/O pin (bank H) — function defined by design
ピン 159 GND — Ground
ピン 160 I/O — User I/O pin (bank H) — function defined by design

主な用途

EPF8636AQC160-5 の用途: 6 件s: Industrial Control Glue Logic, Telecommunications Backplane Bridge, Legacy ASIC Prototyping, PCI Bus Interface Bridge, Test & Measurement Instrumentation Front-End, Avionics Databus Interface (Legacy).

🏭

Industrial Control Glue Logic

The EPF8636AQC160-5 fits industrial control glue logic by offering 504 logic cells and 636 flip-flops in a 5 V-tolerant PQFP-160 package that integrates directly with legacy 5 V PLC backplanes. Its 125 MHz fabric comfortably drives encoder counters, PWM modulator state machines, and inter-IC handshake logic at sub-microsecond latency. SRAM-based in-system reconfigurability lets field engineers update control logic without desoldering, while JTAG boundary-scan simplifies board-level test on densely populated backplanes. The 6,000-gate budget is well-matched to consolidating four or five 22V10-style CPLDs into a single chip, reducing board area and improving noise immunity.

おすすめ

EPC1PC8 · Altera EPF8452AQC160-5 · Altera
🌐

Telecommunications Backplane Bridge

The EPF8636AQC160-5 suits telecom backplane bridging where the device must arbitrate between E1/T1 framers, route HDLC channels, and present a clean interface to an upstream processor. Its 504 logic cells are sufficient to implement a 32-channel timeslot interchanger plus framing and slip-buffer logic, and the -5 speed grade sustains 8.192 MHz backplane operation with timing margin. 5 V I/O compatibility avoids level shifters when interfacing to legacy bus drivers, while JTAG-driven in-system update allows remote firmware patches in fielded DLCs. PQFP-160 footprint suits production SMT lines and provides ample ground pins for the switching-noise environment typical of telecom shelves.

おすすめ

DS2155 (Single-chip E1/T1 framer commonly bridged to FLEX 8000 fabric) EPC1064 (Altera configuration PROM with sufficient density for 8K-gate class FPGAs)
🔧

Legacy ASIC Prototyping

The EPF8636AQC160-5 is a proven vehicle for prototyping legacy ASIC designs that the original design team specified in FLEX 8000 fabric before tape-out. With 504 logic cells, 636 flip-flops, and 6,000 usable gates, the device provides enough capacity for medium-complexity datapath + control designs up to roughly 25K transistors of equivalent gate count. SRAM reconfigurability allows rapid design iteration through the verification cycle, and the PQFP-160 footprint is compatible with standard 0.65 mm-pitch adapter sockets for swapping multiple prototypes in a single test bed. Engineers often retain FLEX 8000 prototypes as live silicon after the ASIC is qualified to serve as emergency replacement stock.

おすすめ

EPC1PC8 · Altera EPF8636AQC160-5N (RoHS drop-in alternate for modern prototype assemblies)
🖥️

PCI Bus Interface Bridge

The EPF8636AQC160-5 fits PCI bridge and endpoint implementations at the 33 MHz, 32-bit PCI 2.1 bus rate, where its -5 speed grade comfortably closes timing on the 7.5 ns Tsu/Th window. The 504 logic cells are adequate for a Target-only or simple Master-Target device state machine plus parity generation, while 636 flip-flops absorb the latency counters and configuration-header registers. 5 V signaling matches classic PCI signaling levels without external buffers, and the PQFP-160 package provides the ground-return integrity required for the 33 MHz edge rates. Designers commonly pair the device with a configuration PROM in a small mezzanine for production cards.

おすすめ

AMCC5920 (Companion PCI arbiter frequently bridged to FLEX 8000 endpoint logic) EPC1064 (Configuration PROM sized for 8K-class FLEX 8000 bitstreams)
🔬

Test & Measurement Instrumentation Front-End

The EPF8636AQC160-5 is well-suited to test-and-measurement front-ends that require custom timing generators, scan controllers, or stimulus-pattern sequencers. Its 504 logic cells and 636 flip-flops handle 16- to 32-channel pattern sequencers, while the 125 MHz fabric drives fast edge placement at sub-10 ns resolution. 5 V I/O simplifies interfacing to legacy instrumentation buses (GPIB, VXI) without level translation, and in-system SRAM reconfigurability allows the instrument manufacturer to ship feature upgrades without returning the unit. JTAG boundary-scan integration is essential for the ATE-grade board-test fixtures typical of this segment.

おすすめ

EPC1PC8 · Altera EPF8452AQC160-5 · Altera
✈️

Avionics Databus Interface (Legacy)

The EPF8636AQC160-5 has been used for MIL-STD-1553 and ARINC 429 databus interface cards where its 504 logic cells encode/decode the protocol state machines and buffer the time-tag counters. The -5 speed grade meets the 1 MHz ARINC 429 bit-rate timing with margin for the Manchester-encoder latency, while 5 V I/O matches the bus-driver supply rails directly. PQFP-160 package fits standard 6U VME / VXI card outlines. Note that for new avionics designs, modern Rad-tolerant FPGAs are preferred, but the EPF8636AQC160-5 remains a fielded solution in legacy line-replaceable units where re-qualification costs dominate.

おすすめ

HI-8588 (ARINC 429 line driver commonly paired with FLEX 8000 encoder) EPC1064 (Configuration PROM for production-grade firmware storage)

おすすめ製品の概要

EPC1PC8 Altera 使用用途: Industrial Control Glue Logic, Legacy ASIC Prototyping, Test & Measurement Instrumentation Front-End EPF8452AQC160-5 Altera 使用用途: Industrial Control Glue Logic, Test & Measurement Instrumentation Front-End DS2155 Single-chip E1/T1 framer commonly bridged to FLEX 8000 fabric 使用用途: Telecommunications Backplane Bridge EPC1064 Altera configuration PROM with sufficient density for 8K-gate class FPGAs 使用用途: Telecommunications Backplane Bridge, PCI Bus Interface Bridge, Avionics Databus Interface (Legacy) EPF8636AQC160-5N RoHS drop-in alternate for modern prototype assemblies 使用用途: Legacy ASIC Prototyping AMCC5920 Companion PCI arbiter frequently bridged to FLEX 8000 endpoint logic 使用用途: PCI Bus Interface Bridge HI-8588 ARINC 429 line driver commonly paired with FLEX 8000 encoder 使用用途: Avionics Databus Interface (Legacy)
What is the logic capacity of EPF8636AQC160-5?
The EPF8636AQC160-5 contains 504 logic cells (LCs), 6,000 usable gates, and 636 flip-flops. According to the Altera FLEX 8000 datasheet family, this places it in the mid-density tier of the FLEX 8000 family, well-suited for glue logic, state machines, and bus-interface designs where modern high-density FPGAs would be overkill but a CPLD lacks sufficient logic resources.
What is the maximum operating frequency of EPF8636AQC160-5?
The EPF8636AQC160-5 supports system clock frequencies up to 125 MHz in the -5 speed grade. Per the Altera FLEX 8000 family datasheet, actual achievable frequency depends on the design's logic depth and routing, but the -5 bin is the fastest grade offered for the EPF8636 die, making it suitable for many 33 MHz and 66 MHz bus-interface applications of its era.
Does EPF8636AQC160-5 require a configuration PROM?
Yes, the EPF8636AQC160-5 uses SRAM-based configuration and requires an external configuration device (such as the Altera EPC1 or EPC1064) or a microcontroller to load the bitstream at power-up. The configuration data is volatile, so the FPGA must be reconfigured after every power cycle unless the configuration source remains active on the board.
What is the difference between EPF8636AQC160-5 and EPF8636AQC160-4?
The EPF8636AQC160-5 is the -5 speed grade (fastest), while the EPF8636AQC160-4 is the -4 speed grade (slightly slower). Both share the same PQFP-160 package, 504 logic cells, 636 flip-flops, and 5 V core. The -5 grade is preferred when timing closure is tight; the -4 grade is typically lower cost and adequate for slower designs.
Where can I buy EPF8636AQC160-5 today?
The EPF8636AQC160-5 is obsolete, but stock is available through specialist distributors including Jotrin, Win Source, Vemeko, IC-Components, Veswin, and Ariat-Tech. Pricing as of 2026-09-12 starts around USD 28.50 at qty-1. Expect longer lead times than current-generation parts and verify each distributor's authenticity warranty before purchase.
What is the lead time for EPF8636AQC160-5?
Lead time for EPF8636AQC160-5 depends on distributor stock and lot availability as of 2026-09-12. Many obsolete distributors quote 4-12 weeks for factory-dated stock, while in-shelf inventory from brokers can ship same-day but at a premium. Always request a date code with the quote and inspect the MSL rating before reflow.
Is EPF8636AQC160-5 in stock at major distributors?
As of 2026-09-12, EPF8636AQC160-5 is not stocked by major franchised distributors such as DigiKey or Mouser because the part is obsolete. Inventory exists primarily at specialist obsolete-component brokers and authorized aftermarket distributors. Check real-time stock via Octopart, which aggregates availability across multiple vendors.
EPF8636AQC160-5 vs EPF8636AQC160-5N — which should I choose?
The EPF8636AQC160-5N is the lead-free / RoHS-compliant variant of the EPF8636AQC160-5. Choose EPF8636AQC160-5N for RoHS-compliant assemblies and modern reflow profiles; choose EPF8636AQC160-5 only when matching a legacy non-RoHS bill of materials. Both share the same PQFP-160 footprint and 504 LC / 636 FF logic resources.
What is the best drop-in replacement for EPF8636AQC160-5?
The closest drop-in replacement for EPF8636AQC160-5 in the same PQFP-160 footprint is the EPF8636AQC160-5N (RoHS variant) or the EPF8636AQC160-4 / EPF8636AQC160-4N (slower -4 speed grade). All four parts share identical pinout and die; only speed grade and lead-finish differ, so substitution requires no PCB rework.
When should I choose EPF8636AQC160-5 over a modern Cyclone FPGA?
Choose EPF8636AQC160-5 only when maintaining a legacy design that cannot be re-qualified, when replacing failed boards in fielded equipment, or when the bitstream is locked to the FLEX 8000 architecture. For new designs, a modern Cyclone IV or Cyclone 10 LP device offers dramatically higher density, lower power, and modern tool support at lower cost.
Where to download EPF8636AQC160-5 datasheet PDF?
The EPF8636AQC160-5 datasheet is available from the Altera FLEX 8000 family datasheet (DSDF8000) hosted on Intel's Altera documentation archive. As of 2026-09-12, the canonical URL is https://www.altera.com/literature/ds/dsf8000.pdf. You may also find the family datasheet mirrored at FPGAkey and other FPGA-focused archives.
Where can I find the EPF8636AQC160-5 pinout?
The complete PQFP-160 pinout for EPF8636AQC160-5 is provided in the Altera FLEX 8000 family datasheet. Pin functions include dedicated configuration pins (nCONFIG, nSTATUS, CONF_DONE, DCLK, DATA0), JTAG pins (TDI, TDO, TMS, TCK), user I/O banks, and global clock/clear buffers. Refer to the datasheet pin tables for the exact PQFP-160 ball-out.
What are the key specifications of EPF8636AQC160-5 that engineers should know?
The EPF8636AQC160-5 integrates 504 logic cells, 636 flip-flops, 6,000 usable gates, and supports up to 125 MHz operation in the -5 speed grade. It uses 5 V core supply with 3.3 V / 5 V configurable I/O, is built on a 0.42 µm CMOS SRAM process, and ships in a PQFP-160 package. Configuration is volatile via JTAG or an external EPC-series configuration PROM.
Is EPF8636AQC160-5 the same as EPF8452AQC160-5?
No. The EPF8636AQC160-5 (6,000 gates, 504 LCs) is a larger FLEX 8000 device than the EPF8452AQC160-5 (4,000 gates, 336 LCs). Both share the PQFP-160 package, so footprint-compatibility is preserved, but bitstreams are NOT interchangeable. The EPF8636 has 50% more logic and is the correct choice when EPF8452 capacity is exceeded.
What is the price of EPF8636AQC160-5 in 2026?
As of 2026-09-12, EPF8636AQC160-5 pricing starts at approximately USD 28.50 per unit at qty-1, decreasing to about USD 14.95 per unit at qty-1000 across specialist obsolete-component distributors. Prices reflect scarcity rather than production cost; expect negotiation room at higher volumes, and always verify date code and RoHS status before PO release.

エンジニアリング参考データ: EPF8636AQC160-5 — 比較、設計ガイダンス、コンプライアンス情報。

選定ガイド

Choose the EPF8636AQC160-5 when maintaining a legacy FLEX 8000 design that requires the fastest speed grade and tolerates a leaded finish. Choose EPF8636AQC160-5N for the same design but in a RoHS-compliant assembly. Choose EPF8636AQC160-4 when timing closure is achievable at the -4 grade (typically ~10-15% slower) and a lower unit price is preferred. Choose EPF8636AQC160-3 for cost-sensitive designs at the slowest speed grade. Choose EPF8452AQC160-5 only when the design fits within 336 LCs / 4K gates — the smaller die is cheaper but not interchangeable at the bitstream level. For new designs, evaluate modern Cyclone IV or Cyclone 10 LP devices, which offer higher density at lower cost.

代替品との比較

パラメータ この製品 EPF8636AQC160-5N EPF8636AQC160-4 EPF8636AQC160-3 EPF8452AQC160-5
Package PQFP-160 PQFP-160 — same PQFP-160 — same PQFP-160 — same PQFP-160 — same
Brand Intel (Altera) Intel (Altera) Intel (Altera) Intel (Altera) Intel (Altera)
Family FLEX 8000 FLEX 8000 FLEX 8000 FLEX 8000 FLEX 8000
Usable Gates 6,000 6,000 6,000 6,000 4,000
Logic Cells 504 504 504 504 336
Flip-Flops 636 636 636 636 452
Speed Grade -5 (fastest) -5 -4 (slower) -3 (slowest) -5 (different die)
Lead-Free / RoHS Leaded (verify per lot) Yes (lead-free, RoHS) Leaded Leaded Leaded
Approx. Unit Price (qty-1, USD, 2026-09-12) 28.50 29.80 22.40 18.90 21.75

主な差別化要因

  • Fastest speed grade within the EPF8636 PQFP-160 family （vs EPF8636AQC160-4)
  • Mid-density sweet spot in the FLEX 8000 family （vs EPF8452AQC160-5)
  • Proven long-term field deployment in industrial and telecom （vs EPF8636AQC160-5N)

設計ノート

The EPF8636AQC160-5 requires two supply rails: VCCINT = 5 V for the core logic and VCCIO = 3.3 V or 5 V for the I/O banks (configurable per bank). Place a 0.1 µF decoupling capacitor within 3 mm of every VCC and VCCIO pin, and add a 10 µF bulk tantalum or ceramic capacitor near the package. Estimated: at 100% utilization of 504 LCs at 125 MHz, expect roughly 0.5-1.0 A from VCCINT and I/O current depends on switching frequency and load — verify with the FLEX 8000 power estimator in the Altera MAX+PLUS II toolchain.

PQFP-160 has 0.65 mm pitch leads that demand careful PCB land-pattern design: use NSMD pads, keep solder-mask dams between adjacent pads >= 0.2 mm wide, and ensure the copper-pour escape pattern does not neck below 0.15 mm. Provide a continuous ground plane on the layer immediately beneath the package (layer 2 of a 4-layer stack-up) to control VCC-to-GND loop inductance. Stencil aperture should be 1:1 to the pad with a 0.1 mm reduction for fine-pitch QFP packages to prevent solder bridging.

Do not leave the FLEX 8000 configuration pins floating — nCONFIG must be tied to VCC through a 10 kΩ pull-up, and nSTATUS, CONF_DONE, and INIT_DONE are open-drain and require external pull-ups to VCCIO. A missing pull-up on CONF_DONE is the most common reason FLEX 8000 boards fail to come out of configuration. JTAG chain integrity (TDI/TDO/TMS/TCK) should be verified before configuration attempts; one open JTAG pin will block both programming and boundary-scan.

PQFP-160 packages have a θJA of approximately 35-45 °C/W depending on PCB copper area. Estimated: at 1 W total dissipation, junction-to-ambient rise is 35-45 °C. For designs operating at industrial temperature (85 °C ambient), ensure PCB copper pour under the package provides at least 1 sq inch of continuous VCC/GND plane to keep junction temperature within the 125 °C commercial limit. Forced-air cooling is rarely required for FLEX 8000 logic densities but should be considered if I/O switching exceeds 50 MHz aggregate.

Global clock pins GCLK1/GCLK2/GCLK3 drive low-skew clock trees inside the FLEX 8000 fabric — route these as 50 Ω controlled-impedance traces with no stubs. Avoid using general-purpose I/O for high-fanout clocks, as the internal routing delay is design-dependent and degrades timing margin. Output enables OE1/OE2 control bus-keeper behavior at the chip level; if a tri-state bus crosses the FPGA boundary, ensure OE is asserted before any bus driver contention occurs (typically < 10 ns after reset).

コンプライアンス情報

RoHS
Non Compliant
REACH
Unknown
AEC-Q100
Not Qualified
鉛フリー
No
ハロゲンフリー
Unknown
紛争鉱物
Unknown

Standard EPF8636AQC160-5 is supplied with a leaded finish (non-RoHS). For RoHS-compliant assemblies, choose the EPF8636AQC160-5N variant. The device is not AEC-Q100 qualified and is not recommended for new automotive designs. Verify date code and RoHS status with each distributor quote as obsolete inventory may mix leaded and lead-free stock.

データ検証日: 2026-09-12 — データはXAIPARTの部品エンジニアリングチームによって検証・管理されています

関連検索

EPF8636AQC160-5 EPF8636AQC160-5 datasheet Altera FLEX 8000 EPF8636 FLEX 8000 PQFP-160 FPGA 6K gates EPF8636 504 logic cells 636 flip-flops EPF8636AQC160-5 pinout PQFP-160 EPF8636 obsolete Altera FPGA replacement EPF8636AQC160-5 vs EPF8636AQC160-5N EPF8636AQC160-5 vs EPF8452AQC160-5 buy EPF8636AQC160-5 obsolete stock EPF8636AQC160-5 price 2026 FLEX 8000 drop-in replacement PQFP-160 what is FLEX 8000 FPGA family EPF8636 configuration PROM EPC1

関連部品&用語

Intel Altera EPF8636AQC160-5 EPF8636AQC160-5N EPF8636AQC160-4 EPF8636AQC160-4N EPF8636AQC160-3 EPF8636AQC160-3N EPF8452AQC160-5 FLEX 8000 FPGA field-programmable gate array programmable logic device PLD CPLD logic cell logic element flip-flop look-up table SRAM configuration JTAG IEEE 1149.1 boundary-scan PQFP-160 plastic quad flat pack surface mount CMOS 0.42 µm process 5V logic 3.3V I/O PCI bus MIL-STD-1553 ARINC 429 industrial control telecom backplane glue logic ASIC prototyping EPC1 EPC1064 configuration PROM RoHS lead-free MAX+PLUS II Quartus AEC-Q100
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