EPF8636AQC160-4N - FLEX 8000 FPGA 6K Gates 504 Cells | Intel
MPN: EPF8636AQC160-4N β End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $78.5 | $78.50 |
| 10 | $72.1 | $721.00 |
| 100 | $65.4 | $6,540.00 |
| 500 | $58.75 | $29,375.00 |
| 1,000 | $52.3 | $52,300.00 |
Drop-in alternatives for EPF8636AQC160-4N β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
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View Datasheet βEPF8636AQC160-4N Maximum Ratings & Electrical Characteristics
| Family | FLEX 8000 |
| Logic Cells / Elements | 504 |
| Usable Gates | 6,000 (typical) |
| User I/Os | 118 |
| Package | 160-pin PQFP (Plastic Quad Flat Pack) |
| Process Technology | 0.42 Β΅m CMOS SRAM |
| Supply Voltage (VCCINT / VCCIO) | 5 V |
| I/O Logic Compatibility | 5.0 V and 3.3 V |
| Maximum Internal Frequency | 125 MHz |
| Typical Fmax (register-rich) | 83 MHz |
| Configuration Method | SRAM, loaded from parallel EPROM or serial EPC1/EPC1064/EPC1213/EPC1441 |
| Boundary-Scan Test | JTAG IEEE Std. 1149.1-1990 (on selected devices) |
| Bus Compliance | PCI Local Bus Specification (PCI SIG) |
| Operating Temperature | 0 Β°C to +70 Β°C (Commercial) |
| In-Circuit Reconfigurability | Yes (ICR) |
| Mounting Type | Surface Mount (gull-wing leads) |
| RoHS Status | unknown |
EPF8636AQC160-4N Pin Configuration
| Pin 1 | I/O β User I/O pin |
| Pin 2 | I/O β User I/O pin |
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| Pin 10 | I/O β User I/O pin |
| Pin 11 | VCC β 5 V supply (per datasheet) |
| Pin 12 | I/O β User I/O pin |
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| Pin 21 | GND β Ground (per datasheet) |
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| Pin 31 | VCC β 5 V supply (per datasheet) |
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| Pin 41 | GND β Ground (per datasheet) |
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| Pin 51 | VCC β 5 V supply (per datasheet) |
| Pin 52 | I/O β User I/O pin |
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| Pin 60 | I/O β User I/O pin |
| Pin 61 | GND β Ground (per datasheet) |
| Pin 62 | I/O β User I/O pin |
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| Pin 70 | I/O β User I/O pin |
| Pin 71 | VCC β 5 V supply (per datasheet) |
| Pin 72 | I/O β User I/O pin |
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| Pin 81 | GND β Ground (per datasheet) |
| Pin 82 | I/O β User I/O pin |
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| Pin 90 | I/O β User I/O pin |
| Pin 91 | VCC β 5 V supply (per datasheet) |
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| Pin 100 | I/O β User I/O pin |
| Pin 101 | GND β Ground (per datasheet) |
| Pin 102 | I/O β User I/O pin |
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| Pin 110 | I/O β User I/O pin |
| Pin 111 | VCC β 5 V supply (per datasheet) |
| Pin 112 | I/O β User I/O pin |
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| Pin 120 | I/O β User I/O pin |
| Pin 121 | GND β Ground (per datasheet) |
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| Pin 130 | I/O β User I/O pin |
| Pin 131 | VCC β 5 V supply (per datasheet) |
| Pin 132 | I/O β User I/O pin |
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| Pin 138 | I/O β User I/O pin |
| Pin 139 | I/O β User I/O pin |
| Pin 140 | I/O β User I/O pin |
| Pin 141 | TDI β JTAG Test Data In (per datasheet, on selected devices) |
| Pin 142 | I/O β User I/O pin (dedicated JTAG routing on selected devices) |
| Pin 143 | I/O β User I/O pin |
| Pin 144 | I/O β User I/O pin |
| Pin 145 | TMS β JTAG Test Mode Select (per datasheet) |
| Pin 146 | I/O β User I/O pin |
| Pin 147 | I/O β User I/O pin |
| Pin 148 | I/O β User I/O pin |
| Pin 149 | I/O β User I/O pin |
| Pin 150 | I/O β User I/O pin |
| Pin 151 | TCK β JTAG Test Clock (per datasheet) |
| Pin 152 | I/O β User I/O pin |
| Pin 153 | I/O β User I/O pin |
| Pin 154 | I/O β User I/O pin |
| Pin 155 | I/O β User I/O pin |
| Pin 156 | I/O β User I/O pin |
| Pin 157 | I/O β User I/O pin |
| Pin 158 | I/O β User I/O pin |
| Pin 159 | TDO β JTAG Test Data Out (per datasheet) |
| Pin 160 | nCONFIG β Configuration start / reset (per datasheet) |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPF8636AQC160-4N is suitable for 6 applications: PCI Bus Interface Bridge, Industrial Glue Logic Replacement, Legacy Telecom Backplane Controller, JTAG-Based Prototyping Platform, VME / CPCI Legacy Slot Card, Test and Measurement Front-End.
PCI Bus Interface Bridge
The EPF8636AQC160-4N is purpose-built for PCI Local Bus Specification-compliant bridges in legacy industrial PCs and embedded backplanes. Its PCI SIG compliance and 5 V / 3.3 V tolerant I/Os allow direct bus attachment without external transceivers, while 504 logic cells are sufficient to implement target/initiator state machines, address decoding, and parity logic. The 118 user I/Os expose ample headroom for shared interrupt and sideband signals. Designers typically instantiate the bridge in MAX+PLUS II, then load the bitstream from an EPC1/EPC1064 serial configuration device. Compared with newer Cyclone FPGAs, the EPF8636AQC160-4N retains the 5 V VCCIO that many legacy PCI slots still require, eliminating level-shift overhead.
Recommended
Industrial Glue Logic Replacement
The EPF8636AQC160-4N serves as a single-chip replacement for dozens of 74-series glue-logic devices on legacy industrial control boards. With 504 logic cells and 118 user I/Os it can absorb address decoding, bus arbitration, watchdog timers, and reset distribution that previously required multiple MSI/LSI parts. Its 5 V tolerant I/Os interface directly to legacy 74LS/74HC logic, and JTAG boundary-scan (IEEE 1149.1-1990) simplifies board-test routines on the production line. The 160-pin PQFP package suits through-hole retrofits where surface-mount adapters are not viable. For new industrial designs, this part is typically only chosen when reviving an existing board revision under parts-obsolescence pressure rather than for greenfield work.
Recommended
Legacy Telecom Backplane Controller
The EPF8636AQC160-4N is commonly deployed as a backplane controller in legacy telecom shelves where 5 V signalling and PCI-like parallel buses are still in service. Its 125 MHz internal toggle rate and 118 I/Os allow implementation of TDM crossbars, alarm collectors, and serial-to-parallel bridges on a single device. SRAM-based configuration permits remote in-circuit reconfigurability (ICR) for field firmware updates without board swap. The 0 Β°C to 70 Β°C commercial temperature range suits controlled-environment central-office deployments. Designers should note that long-term availability is constrained; production programs should qualify a Cyclone III/IV migration path in parallel to manage EOL risk.
Recommended
JTAG-Based Prototyping Platform
The EPF8636AQC160-4N is a strong fit for university and R&D prototyping boards that use JTAG (IEEE 1149.1-1990) for both configuration and boundary-scan test. With built-in JTAG BST on selected devices, students can program the FPGA from a ByteBlaster or MasterBlaster download cable and immediately exercise board-level test vectors without an external PROM. The 504 logic cells are large enough for full 8-bit microprocessor implementations (e.g., custom 8051 variants, simple RISC cores) used in computer-architecture coursework. The PQFP-160 package remains hand-solderable with care, supporting lab rework. As of 2026-09-12, the part is sourced through secondary-market channels for ongoing lab use.
Recommended
VME / CPCI Legacy Slot Card
The EPF8636AQC160-4N is widely used on legacy VMEbus and CompactPCI peripheral cards where 5 V signalling and PCI compliance are mandatory. Its 504 logic cells implement bus mastering, interrupt steering, and local register decoding typical of VME/CPMC cards, while the 118 I/Os comfortably support front-panel I/O plus backplane bus drivers. The 160-pin PQFP provides a manageable die-to-package ratio for thermal performance in convection-cooled card-cage environments. Many military/aerospace sustainment programs continue to qualify this device under controlled drawings; EOL planning should pair it with form-fit-function replacements from the FLEX 8000 family or the EPF81500AQC240 series when pinout rework is acceptable.
Recommended
Test and Measurement Front-End
The EPF8636AQC160-4N is well suited to legacy test-and-measurement front-ends such as logic-analyzer pods, pattern-generator channels, and boundary-scan controllers. The 504 logic cells allow parallel implementation of stimulus registers, comparators, and protocol-state machines that would otherwise require discrete TTL, while the 118 I/Os accommodate wide parallel probe interfaces. JTAG BST (IEEE 1149.1-1990) compliance simplifies integration into ATE fixtures. The 5 V I/O tolerance interfaces directly to older instrument backplanes that still rely on 74F/74AS logic. Engineers modernizing these instruments should note that this device supports the full IEEE 1149.1 boundary-scan instruction set including EXTEST, SAMPLE/PRELOAD, and BYPASS.
Recommended
Recommended Products Summary
Engineering reference data for EPF8636AQC160-4N β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPF8636AQC160-4 | EPF8636AQC160-3N | EPF8636AQC160-3 | EPF8452AQC160-4N | EPF8452AQC160-4 |
|---|---|---|---|---|---|---|
| Brand | Intel (formerly Altera) | Intel | Intel | Intel | Intel | Intel |
| Package | 160-pin PQFP | 160-pin PQFP - same | 160-pin PQFP - same | 160-pin PQFP - same | 160-pin PQFP - same | 160-pin PQFP - same |
| Usable Gates | 6,000 | 6,000 (same) | 6,000 (same) | 6,000 (same) | 4,000 (-33%) | 4,000 (-33%) |
| Logic Cells / Elements | 504 | 504 (same) | 504 (same) | 504 (same) | 336 (-33%) | 336 (-33%) |
| Speed Grade | -4 | -4 (same) | -3 (slower) | -3 (slower) | -4 (same) | -4 (same) |
| Supply Voltage | 5 V | 5 V | 5 V | 5 V | 5 V | 5 V |
| User I/Os | 118 | 118 | 118 | 118 | 120 | 120 |
| JTAG (IEEE 1149.1) | Yes (selected devices) | Yes | Yes | Yes | Yes | Yes |
| PCI Compliance | Yes | Yes | Yes | Yes | Yes | Yes |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
Key Differentiators
- Highest logic density within FLEX 8000 PQFP-160 family (vs EPF8452AQC160-4N)
- Speed grade -4 delivers faster Fmax than speed grade -3 (vs EPF8636AQC160-3N)
- Built-in JTAG boundary-scan (IEEE 1149.1-1990) (vs EPF8636AQC160-3N)
Design Notes
Estimated: at 5 V VCC with 50% toggle rate on all 118 user I/Os, I/O current draw is dominated by capacitive load charging. Use bulk decoupling of 100 Β΅F tantalum plus 0.1 Β΅F ceramic per VCC pin, and place a 1 Β΅F tantalum near each VCCINT pin. The FLEX 8000 datasheet recommends placing one decoupling capacitor within 5 mm of every VCC/GND pin pair. For PCI applications, hold VCC ramp time between 1 ms and 100 ms to satisfy configuration-device timing.
Do not assume all 160 PQFP pins are user I/O - the EPF8636AQC160-4N dedicates specific pins to JTAG (TCK, TMS, TDI, TDO), configuration (nCONFIG, CONF_DONE, nSTATUS), and power (VCCINT, VCCIO, GND). Pulling CONF_DONE high through a 10 kΞ© resistor and driving nCONFIG from a clean POR supervisor prevents spontaneous reconfiguration on noisy 5 V rails. Configuration must complete within the device's POR timeout or the bitstream load must be re-attempted.
The 160-pin PQFP has 0.65 mm pitch leads; route all signals on inner layers with 0.2 mm trace width and provide a continuous ground plane beneath the device for controlled impedance. Keep JTAG trace lengths below 50 mm to avoid signal-integrity issues. For production boards, expose JTAG header pins (TCK, TMS, TDI, TDO, GND) to enable in-system programming via ByteBlasterMV or MasterBlaster cables.
Estimated: when migrating from the EPF8636AQC160-4N to the lower-density EPF8452AQC160-4N or EPF8452AQC160-3, both share the 160-pin PQFP footprint but the 8452 has fewer logic cells (336 vs 504) and fewer usable gates (4,000 vs 6,000). Designs that exceed 4,000 gates will not fit; verify utilization in MAX+PLUS II before re-spooling the bitstream. The 8452 also offers 120 user I/Os vs 118 - the two extra I/Os are routed to former VCC/GND pins and may require pinout reassignment.
Compliance Information
Compliance data not present in the verified web data; the EPF8636AQC160-4N is a 1990s-era legacy device whose original PQFP package was typically leaded (SnPb). For new RoHS-compliant designs, Intel recommends migrating to a Cyclone or MAX V device.
