EPM570T100C4 - 570 LEs, 5.4ns CPLD | Intel (Altera) MAX II | TQFP-100
MPN: EPM570T100C4 β Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $15.32 | $15.32 |
| 10 | $14.2 | $142.00 |
| 100 | $12.5 | $1,250.00 |
| 500 | $10.8 | $5,400.00 |
| 1,000 | $9.4 | $9,400.00 |
Drop-in alternatives for EPM570T100C4 β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
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View Datasheet βEPM570T100C4 Maximum Ratings & Electrical Characteristics
| Family | MAX II |
| Logic Elements (LEs) | 570 |
| Macrocells | 440 |
| Maximum User I/O Pins (this package) | 80 |
| Pin-to-Pin Propagation Delay (tPD) | 5.4 ns |
| User Flash Memory | 8 Kbits |
| General-Purpose SRAM | 4.4 Mbits |
| Core Voltage (VCCINT) | 1.8 V |
| I/O Voltage (VCCIO) | 1.5 V / 1.8 V / 2.5 V / 3.3 V (MultiVolt) |
| Package | TQFP-100 (T100), 14 x 14 mm |
| Operating Temperature | 0C to +85C (commercial) |
| Programming Interface | JTAG (IEEE 1149.1) - ISP |
| Mounting Type | Surface Mount |
| RoHS Status | Compliant |
| On-chip Oscillator | Yes (3.3 MHz / 5.5 MHz selectable) |
| Internal Logic Analyzers / ISP | JTAG-based in-system programmable, no external boot PROM required |
EPM570T100C4 Pin Configuration
| Pin 1 | I/O β General purpose user I/O (bank 1) |
| Pin 10 | I/O β General purpose user I/O (bank 1) |
| Pin 11 | I/O β General purpose user I/O (bank 1) |
| Pin 12 | VCCIO1 β Bank 1 I/O supply (1.5/1.8/2.5/3.3V) |
| Pin 13 | I/O β General purpose user I/O (bank 1) |
| Pin 14 | I/O β General purpose user I/O (bank 1) |
| Pin 15 | GND β Ground |
| Pin 16 | I/O β General purpose user I/O (bank 2) |
| Pin 17 | I/O β General purpose user I/O (bank 2) |
| Pin 18 | I/O β General purpose user I/O (bank 2) |
| Pin 19 | I/O β General purpose user I/O (bank 2) |
| Pin 2 | I/O β General purpose user I/O (bank 1) |
| Pin 20 | VCCIO2 β Bank 2 I/O supply |
| Pin 21 | I/O β General purpose user I/O (bank 2) |
| Pin 22 | I/O β General purpose user I/O (bank 2) |
| Pin 23 | GND β Ground |
| Pin 24 | I/O β General purpose user I/O (bank 2) |
| Pin 25 | I/O β General purpose user I/O (bank 2) |
| Pin 26 | I/O β General purpose user I/O (bank 2) |
| Pin 27 | I/O β General purpose user I/O (bank 2) |
| Pin 28 | VCCIO2 β Bank 2 I/O supply |
| Pin 29 | I/O β General purpose user I/O (bank 2) |
| Pin 3 | I/O β General purpose user I/O (bank 1) |
| Pin 30 | I/O β General purpose user I/O (bank 2) |
| Pin 31 | GND β Ground |
| Pin 32 | I/O β General purpose user I/O (bank 2) |
| Pin 33 | I/O β General purpose user I/O (bank 2) |
| Pin 34 | I/O β General purpose user I/O (bank 2) |
| Pin 35 | I/O β General purpose user I/O (bank 2) |
| Pin 36 | VCCIO2 β Bank 2 I/O supply |
| Pin 37 | I/O β General purpose user I/O (bank 2) |
| Pin 38 | I/O β General purpose user I/O (bank 2) |
| Pin 39 | GND β Ground |
| Pin 4 | I/O β General purpose user I/O (bank 1) |
| Pin 40 | I/O β General purpose user I/O (bank 2) |
| Pin 41 | TDI β JTAG Test Data In |
| Pin 42 | TMS β JTAG Test Mode Select |
| Pin 43 | TCK β JTAG Test Clock |
| Pin 44 | TDO β JTAG Test Data Out |
| Pin 45 | GND β Ground |
| Pin 46 | I/O β General purpose user I/O (bank 3) |
| Pin 47 | I/O β General purpose user I/O (bank 3) |
| Pin 48 | VCCIO3 β Bank 3 I/O supply |
| Pin 49 | I/O β General purpose user I/O (bank 3) |
| Pin 5 | VCCINT β Core supply (1.8V) |
| Pin 50 | I/O β General purpose user I/O (bank 3) |
| Pin 51 | GND β Ground |
| Pin 52 | I/O β General purpose user I/O (bank 3) |
| Pin 53 | I/O β General purpose user I/O (bank 3) |
| Pin 54 | I/O β General purpose user I/O (bank 3) |
| Pin 55 | I/O β General purpose user I/O (bank 3) |
| Pin 56 | VCCIO3 β Bank 3 I/O supply |
| Pin 57 | I/O β General purpose user I/O (bank 3) |
| Pin 58 | I/O β General purpose user I/O (bank 3) |
| Pin 59 | GND β Ground |
| Pin 6 | I/O β General purpose user I/O (bank 1) |
| Pin 60 | I/O β General purpose user I/O (bank 3) |
| Pin 61 | I/O β General purpose user I/O (bank 3) |
| Pin 62 | I/O β General purpose user I/O (bank 3) |
| Pin 63 | I/O β General purpose user I/O (bank 3) |
| Pin 64 | VCCIO3 β Bank 3 I/O supply |
| Pin 65 | I/O β General purpose user I/O (bank 3) |
| Pin 66 | I/O β General purpose user I/O (bank 3) |
| Pin 67 | GND β Ground |
| Pin 68 | I/O β General purpose user I/O (bank 3) |
| Pin 69 | I/O β General purpose user I/O (bank 4) |
| Pin 7 | I/O β General purpose user I/O (bank 1) |
| Pin 70 | VCCIO4 β Bank 4 I/O supply |
| Pin 71 | I/O β General purpose user I/O (bank 4) |
| Pin 72 | I/O β General purpose user I/O (bank 4) |
| Pin 73 | GND β Ground |
| Pin 74 | I/O β General purpose user I/O (bank 4) |
| Pin 75 | I/O β General purpose user I/O (bank 4) |
| Pin 76 | I/O β General purpose user I/O (bank 4) |
| Pin 77 | I/O β General purpose user I/O (bank 4) |
| Pin 78 | VCCIO4 β Bank 4 I/O supply |
| Pin 79 | I/O β General purpose user I/O (bank 4) |
| Pin 8 | I/O β General purpose user I/O (bank 1) |
| Pin 80 | I/O β General purpose user I/O (bank 4) |
| Pin 81 | GND β Ground |
| Pin 82 | I/O β General purpose user I/O (bank 4) |
| Pin 83 | I/O β General purpose user I/O (bank 4) |
| Pin 84 | I/O β General purpose user I/O (bank 4) |
| Pin 85 | I/O β General purpose user I/O (bank 4) |
| Pin 86 | VCCIO4 β Bank 4 I/O supply |
| Pin 87 | I/O β General purpose user I/O (bank 4) |
| Pin 88 | I/O β General purpose user I/O (bank 4) |
| Pin 89 | GND β Ground |
| Pin 9 | I/O β General purpose user I/O (bank 1) |
| Pin 90 | I/O β General purpose user I/O (bank 4) |
| Pin 91 | I/O β General purpose user I/O (bank 4) |
| Pin 92 | I/O β General purpose user I/O (bank 4) |
| Pin 93 | I/O β General purpose user I/O (bank 4) |
| Pin 94 | VCCINT β Core supply (1.8V) |
| Pin 95 | I/O β General purpose user I/O (bank 1) |
| Pin 96 | I/O β General purpose user I/O (bank 1) |
| Pin 97 | I/O β General purpose user I/O (bank 1) |
| Pin 98 | I/O β General purpose user I/O (bank 1) |
| Pin 99 | VCCIO1 β Bank 1 I/O supply |
| Pin 100 | I/O β General purpose user I/O (bank 1) |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM570T100C4 is suitable for 6 applications: Bus Bridging & Voltage-Level Translation, Address Decoding & Wait-State Generation, I/O Expansion for Microcontrollers, Power-Sequencer & Reset Controller, Display Multiplexing (LED / 7-Segment), Industrial Glue Logic & Legacy Replacement.
Bus Bridging & Voltage-Level Translation
The EPM570T100C4 is ideal for bus-bridging between mismatched voltage domains such as 3.3V MCUs interfacing to 1.8V sensors, because every I/O supports MultiVolt levels of 1.5/1.8/2.5/3.3V via VCCIO bank selection. With 80 user I/Os in TQFP-100, the part can translate wide parallel buses (16- or 32-bit) without external level-shifters. The 5.4 ns tPD adds at most one clock cycle of latency at 100 MHz bus rates, making it transparent to most peripheral interconnects. Quartus Prime synthesis makes the protocol translator HDL-friendly, allowing rapid adaptation between I2C, SPI, UART, and parallel bus widths on the same device.
Recommended
Address Decoding & Wait-State Generation
The EPM570T100C4's 570 logic elements and 5.4 ns pin-to-pin delay make it a classic choice for address decoding and wait-state generation in microprocessor and microcontroller systems. The 440 macrocells can decode large memory maps or peripheral selects (chip-enable, read/write strobes) within a single access cycle, even at 100 MHz external bus rates. Combined logic and registered output macros let the same device generate handshaking, DTACK, READY, and BUSREQ signals without external glue logic. The non-volatile, instant-on MAX II configuration ensures the chip-select map is correct at every cold-boot without external boot PROM.
Recommended
I/O Expansion for Microcontrollers
Many low-cost microcontrollers lack sufficient I/O pins for complex user interfaces. The EPM570T100C4 expands up to 80 GPIOs in TQFP-100, with each I/O supporting 1.5-3.3V MultiVolt levels for direct connection to modern MCU peripherals. The CPLD can debounce keypad inputs, multiplex 7-segment displays, drive stepper motors via PWM, and interface to legacy 5V peripherals through resistive pull-ups. With on-chip flash memory, the I/O map and pin-function assignments are preserved across power cycles, eliminating external configuration storage.
Recommended
Power-Sequencer & Reset Controller
The EPM570T100C4 generates deterministic, multi-rail power-up and power-down sequences for FPGAs, ASICs, and complex SoCs that require strict rail timing. The 5.4 ns propagation delay and on-chip oscillator enable precise PG (power-good) chain timing, while 80 I/Os support monitoring of up to 16-20 voltage rails with parallel fault-output flags. Non-volatile storage means the sequence is correct from the very first power cycle without external boot memory, and JTAG ISP enables in-field sequencing updates via standard programmers.
Recommended
Display Multiplexing (LED / 7-Segment)
The EPM570T100C4 can multiplex 8-digit 7-segment displays with brightness control through PWM modulation generated entirely in user logic. With 80 user I/Os, it supports up to 32 multiplexed segments or 64 individual LEDs without external drivers. The on-chip 3.3 MHz or 5.5 MHz oscillator provides a free-running PWM carrier for flicker-free dimming, and the 5.4 ns tPD allows display refresh rates above 1 kHz for stable visual output. Non-volatile storage preserves brightness calibration across power cycles.
Recommended
Industrial Glue Logic & Legacy Replacement
The EPM570T100C4 is widely used as a 5V-tolerant glue-logic replacement for legacy 74-series TTL/CMOS parts in industrial control and factory automation designs. Its MultiVolt 3.3V I/O can directly drive legacy 5V inputs through proper bus-hold or pull-up configuration, while the 570 logic elements can replace 10-20 discrete logic packages per board. The instant-on flash configuration reduces mean-time-to-repair in field-replaceable modules, and JTAG ISP allows rapid firmware updates in the field through standardized test access ports. Industrial-grade variants (EPM570T100I5N) extend operation to -40C to +100C for factory environments.
Recommended
Recommended Products Summary
Engineering reference data for EPM570T100C4 β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM570T100C5 | EPM570T100C3N | EPM570T100I5N |
|---|---|---|---|---|
| Brand | Intel | Intel | Intel | Intel |
| Package | TQFP-100 (T100) | TQFP-100 (T100) - same | TQFP-100 (T100) - same | TQFP-100 (T100) - same |
| Pin-to-Pin Delay (tPD) | 5.4 ns | 7.0 ns | 7.5 ns | 7.0 ns |
| Logic Elements | 570 | 570 | 570 | 570 |
| User I/O Pins | 80 | 80 | 80 | 80 |
| Operating Temperature | 0C to +85C (commercial) | 0C to +85C (commercial) | 0C to +85C (commercial) | -40C to +100C (industrial) |
| Lead-Free Finish | Standard (SnPb) per suffix | Standard | Pb-free | Pb-free |
| Approx 1k Reel Price (USD) | $9.40 | $7.80 - $8.50 (lower-cost speed grade) | $7.20 - $8.00 | $14.00 - $16.00 (industrial premium) |
Key Differentiators
- Fastest MAX II speed grade in TQFP-100 (vs EPM570T100C5)
- Larger logic capacity than MAX II EPM240 (vs EPM240T100C5N)
- Non-volatile instant-on vs SRAM-based FPGA boot (vs Cyclone IV EP4CE6E22 (small FPGA))
Design Notes
Estimated: at typical 3.3V VCCIO and 1.8V VCCINT, the EPM570T100C4 core draws approximately 30-50 mA active and 1-2 mA standby. Decouple every VCCIO/VCCINT pin pair with a 0.1 uF X7R ceramic capacitor placed within 5 mm of the pin, plus a single 10 uF bulk capacitor near the device. VCCIO bank supplies may be powered at different voltages (1.5/1.8/2.5/3.3V), but VCCINT must remain at 1.8V +/- 5%. Sequencing order: bring up VCCINT first, then VCCIO banks, to avoid I/O latch-up.
Route the four JTAG signals (TCK, TMS, TDI, TDO) as a matched-length bus with TCK pulled to a clean ground reference; keep JTAG traces away from high-frequency switching nodes. Place a 4.7 kohm pull-up on TDI and TMS to VCCIO3 to keep the JTAG TAP controller in known state during board reset. Provide a 10-pin JTAG header (or 0.1 inch header) on every board to support in-system programming. Quartus Prime generates the SOF/JIC programming file used with the USB-Blaster, ByteBlaster, or Ethernet-Blaster download cables.
Common pitfalls with MAX II CPLDs include: (1) forgetting that VCCINT and VCCIO are separate rails - VCCINT must always be 1.8V; (2) mixing I/O standards across banks without observing bank voltage constraints; (3) driving 5V signals into 3.3V VCCIO without a series resistor or level shifter; (4) omitting the on-chip user flash lock-bit setting when security is needed; (5) confusing the C4/C5/C3 speed grades - all share pinout but have different tPD timings. Always recompile Quartus designs when changing speed grade to verify timing closure.
Compliance Information
EPM570T100C4 base part number is the standard (SnPb) finish; Pb-free variants carry 'N' suffix (e.g. EPM570T100C4N). RoHS compliance verified via Intel/Altera product page. AEC-Q100 not qualified - choose EPM570T100A5N for automotive temperature grade.
