EPM570T144C4 - 570 LEs, 116 I/O, 3.3V MAX II CPLD | Intel
部品番号: EPM570T144C4 ✓ 生産中| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $37.66 | $37.66 |
| 10 | $32.5 | $325.00 |
| 100 | $26.8 | $2,680.00 |
| 500 | $22.45 | $11,225.00 |
| 1,000 | $19.2 | $19,200.00 |
EPM570T144C4 概要
A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that combines multiple PAL-like logic blocks on a single chip, providing fast, deterministic propagation delays ideal for implementing combinational and sequential glue logic, state machines, and bus interfaces. Within the broader taxonomy, CPLDs sit alongside FPGAs in the programmable logic hierarchy; however, CPLDs typically have lower logic density, lower power consumption, and instant-on non-volatile configuration - making them complementary to FPGAs rather than competitive.
Key features of the EPM570T144C4 include 570 logic elements, 116 user I/Os (144-pin TQFP), 8 Kbits of user flash memory (UFM), MultiVolt core and I/O support (1.5 V, 1.8 V, 2.5 V, 3.3 V), and in-system programmability (ISP) via JTAG. Propagation delay is rated at 5.4 ns (pin-to-pin, tPD1) with a maximum internal frequency of 304 MHz, providing deterministic timing for asynchronous and high-speed interfaces.
The MAX II architecture eliminates external configuration memory by storing the configuration in on-chip flash, enabling instant-on operation in under 1 ms - a critical feature for power-sequencing and boot-loader designs. The on-chip UFM block provides non-volatile parameter storage (firmware version, calibration data) without requiring a separate EEPROM. MultiVolt I/O supports interfacing directly to 3.3 V, 2.5 V, 1.8 V, and 1.5 V logic families on the same device, simplifying mixed-voltage designs.
Typical applications include bus-bridging between legacy microcontrollers and modern peripherals, I/O expansion via serial-to-parallel or parallel-to-serial conversion, power-on sequencing in multi-rail systems, LED driving matrix controllers, and glue-logic replacement for discrete 74-series logic in commercial and industrial equipment.
When designing with this device, observe the 1.8 V core supply requirement (VCCINT) and 3.3 V I/O supply (VCCIO) - the device does not support 5 V tolerant inputs without external level shifters. Quartus II Web Edition (free) supports MAX II design entry, synthesis, and programming for this part.
This page synthesizes distributor pricing, vertical-migration alternatives, and practical MAX II design notes not aggregated on the manufacturer datasheet.
ドロップイン代替品: EPM570T144C4 — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: EPM570T144C4 （同一形状・フットプリント） — 相違点: Programming Interface, Package, Operating Temperature, Process Technology, I/O Supply Voltage (VCCIO).
クイック比較ツール — 並列比較する代替部品を選択:
EPM570T144C5N
✅ ドロップイン✓ 在庫あり
$9.35 / 個
データシートを見る →EPM570T144C3N
✅ ドロップイン✓ 在庫あり
$9.6 / 個
データシートを見る →EPM570T144A5N
✅ ドロップイン✓ 在庫あり
$22.8 / 個
データシートを見る →EPM570T144-5
✅ ドロップイン✓ 在庫あり
$9.85 / 個
データシートを見る →EPM570T144C4N
✅ ドロップイン✓ 在庫あり
$25.1 / 個
データシートを見る →EPM570T144C4 最大定格＆電気的特性
| Family | MAX II |
| Logic Elements (LEs) | 570 |
| Equivalent Macrocells | 440 |
| Maximum User I/Os | 116 |
| User Flash Memory (UFM) | 8 Kbits |
| Propagation Delay (tPD) | 5.4 ns (fastest speed grade C4) |
| Maximum Internal Frequency | 304 MHz |
| Core Voltage (VCCINT) | 1.8 V (internal) |
| I/O Voltage (VCCIO) | 1.5 V / 1.8 V / 2.5 V / 3.3 V (MultiVolt) |
| 動作温度 | 0C to +85C (commercial extended) |
| パッケージ | 144-pin TQFP (20 mm x 20 mm, 0.5 mm pitch) |
| 実装タイプ | Surface Mount |
| MSLレベル | 3 (168 hours) |
| RoHS ステータス | Compliant |
| Configuration Memory | On-chip flash (non-volatile, instant-on) |
| Programming Interface | JTAG (IEEE 1149.1) - ISP |
EPM570T144C4 ピン構成
| ピン 1 | I/O — User I/O pin (bank 1) |
| ピン 2 | I/O — User I/O pin (bank 1) |
| ピン 3 | I/O — User I/O pin (bank 1) |
| ピン 4 | I/O — User I/O pin (bank 1) |
| ピン 5 | I/O — User I/O pin (bank 1) |
| ピン 6 | I/O — User I/O pin (bank 1) |
| ピン 7 | I/O — User I/O pin (bank 1) |
| ピン 8 | VCCIO1 — I/O supply voltage bank 1 |
| ピン 9 | I/O — User I/O pin (bank 1) |
| ピン 10 | I/O — User I/O pin (bank 1) |
| ピン 11 | GND — Ground |
| ピン 12 | I/O — User I/O pin (bank 1) |
| ピン 13 | I/O — User I/O pin (bank 1) |
| ピン 14 | I/O — User I/O pin (bank 1) |
| ピン 15 | I/O — User I/O pin (bank 1) |
| ピン 16 | I/O — User I/O pin (bank 1) |
| ピン 17 | I/O — User I/O pin (bank 1) |
| ピン 18 | I/O — User I/O pin (bank 1) |
| ピン 19 | I/O — User I/O pin (bank 1) |
| ピン 20 | I/O — User I/O pin (bank 1) |
| ピン 21 | VCCINT — Core supply voltage (1.8 V) |
| ピン 22 | I/O — User I/O pin (bank 1) |
| ピン 23 | I/O — User I/O pin (bank 1) |
| ピン 24 | I/O — User I/O pin (bank 1) |
| ピン 25 | I/O — User I/O pin (bank 1) |
| ピン 26 | I/O — User I/O pin (bank 1) |
| ピン 27 | I/O — User I/O pin (bank 1) |
| ピン 28 | I/O — User I/O pin (bank 1) |
| ピン 29 | I/O — User I/O pin (bank 1) |
| ピン 30 | GND — Ground |
| ピン 31 | I/O — User I/O pin (bank 2) |
| ピン 32 | I/O — User I/O pin (bank 2) |
| ピン 33 | I/O — User I/O pin (bank 2) |
| ピン 34 | I/O — User I/O pin (bank 2) |
| ピン 35 | I/O — User I/O pin (bank 2) |
| ピン 36 | I/O — User I/O pin (bank 2) |
| ピン 37 | VCCIO2 — I/O supply voltage bank 2 |
| ピン 38 | I/O — User I/O pin (bank 2) |
| ピン 39 | I/O — User I/O pin (bank 2) |
| ピン 40 | I/O — User I/O pin (bank 2) |
| ピン 41 | I/O — User I/O pin (bank 2) |
| ピン 42 | I/O — User I/O pin (bank 2) |
| ピン 43 | I/O — User I/O pin (bank 2) |
| ピン 44 | I/O — User I/O pin (bank 2) |
| ピン 45 | TDI — JTAG Test Data In |
| ピン 46 | TMS — JTAG Test Mode Select |
| ピン 47 | TCK — JTAG Test Clock |
| ピン 48 | TDO — JTAG Test Data Out |
| ピン 49 | I/O — User I/O pin (bank 2) |
| ピン 50 | GND — Ground |
| ピン 51 | I/O — User I/O pin (bank 2) |
| ピン 52 | I/O — User I/O pin (bank 2) |
| ピン 53 | I/O — User I/O pin (bank 2) |
| ピン 54 | I/O — User I/O pin (bank 2) |
| ピン 55 | I/O — User I/O pin (bank 2) |
| ピン 56 | I/O — User I/O pin (bank 2) |
| ピン 57 | I/O — User I/O pin (bank 2) |
| ピン 58 | I/O — User I/O pin (bank 2) |
| ピン 59 | I/O — User I/O pin (bank 2) |
| ピン 60 | I/O — User I/O pin (bank 2) |
| ピン 61 | VCCINT — Core supply voltage (1.8 V) |
| ピン 62 | I/O — User I/O pin (bank 2) |
| ピン 63 | I/O — User I/O pin (bank 2) |
| ピン 64 | I/O — User I/O pin (bank 2) |
| ピン 65 | I/O — User I/O pin (bank 2) |
| ピン 66 | I/O — User I/O pin (bank 2) |
| ピン 67 | I/O — User I/O pin (bank 2) |
| ピン 68 | I/O — User I/O pin (bank 2) |
| ピン 69 | I/O — User I/O pin (bank 2) |
| ピン 70 | GND — Ground |
| ピン 71 | I/O — User I/O pin (bank 3) |
| ピン 72 | I/O — User I/O pin (bank 3) |
| ピン 73 | I/O — User I/O pin (bank 3) |
| ピン 74 | I/O — User I/O pin (bank 3) |
| ピン 75 | I/O — User I/O pin (bank 3) |
| ピン 76 | I/O — User I/O pin (bank 3) |
| ピン 77 | VCCIO3 — I/O supply voltage bank 3 |
| ピン 78 | I/O — User I/O pin (bank 3) |
| ピン 79 | I/O — User I/O pin (bank 3) |
| ピン 80 | I/O — User I/O pin (bank 3) |
| ピン 81 | I/O — User I/O pin (bank 3) |
| ピン 82 | I/O — User I/O pin (bank 3) |
| ピン 83 | I/O — User I/O pin (bank 3) |
| ピン 84 | I/O — User I/O pin (bank 3) |
| ピン 85 | I/O — User I/O pin (bank 3) |
| ピン 86 | I/O — User I/O pin (bank 3) |
| ピン 87 | I/O — User I/O pin (bank 3) |
| ピン 88 | I/O — User I/O pin (bank 3) |
| ピン 89 | I/O — User I/O pin (bank 3) |
| ピン 90 | I/O — User I/O pin (bank 3) |
| ピン 91 | VCCINT — Core supply voltage (1.8 V) |
| ピン 92 | I/O — User I/O pin (bank 3) |
| ピン 93 | I/O — User I/O pin (bank 3) |
| ピン 94 | I/O — User I/O pin (bank 3) |
| ピン 95 | I/O — User I/O pin (bank 3) |
| ピン 96 | I/O — User I/O pin (bank 3) |
| ピン 97 | I/O — User I/O pin (bank 3) |
| ピン 98 | I/O — User I/O pin (bank 3) |
| ピン 99 | I/O — User I/O pin (bank 3) |
| ピン 100 | I/O — User I/O pin (bank 3) |
| ピン 101 | GND — Ground |
| ピン 102 | I/O — User I/O pin (bank 4) |
| ピン 103 | I/O — User I/O pin (bank 4) |
| ピン 104 | I/O — User I/O pin (bank 4) |
| ピン 105 | I/O — User I/O pin (bank 4) |
| ピン 106 | I/O — User I/O pin (bank 4) |
| ピン 107 | I/O — User I/O pin (bank 4) |
| ピン 108 | VCCIO4 — I/O supply voltage bank 4 |
| ピン 109 | I/O — User I/O pin (bank 4) |
| ピン 110 | I/O — User I/O pin (bank 4) |
| ピン 111 | I/O — User I/O pin (bank 4) |
| ピン 112 | I/O — User I/O pin (bank 4) |
| ピン 113 | I/O — User I/O pin (bank 4) |
| ピン 114 | I/O — User I/O pin (bank 4) |
| ピン 115 | I/O — User I/O pin (bank 4) |
| ピン 116 | I/O — User I/O pin (bank 4) |
| ピン 117 | I/O — User I/O pin (bank 4) |
| ピン 118 | I/O — User I/O pin (bank 4) |
| ピン 119 | I/O — User I/O pin (bank 4) |
| ピン 120 | I/O — User I/O pin (bank 4) |
| ピン 121 | VCCINT — Core supply voltage (1.8 V) |
| ピン 122 | I/O — User I/O pin (bank 4) |
| ピン 123 | I/O — User I/O pin (bank 4) |
| ピン 124 | I/O — User I/O pin (bank 4) |
| ピン 125 | I/O — User I/O pin (bank 4) |
| ピン 126 | I/O — User I/O pin (bank 4) |
| ピン 127 | I/O — User I/O pin (bank 4) |
| ピン 128 | I/O — User I/O pin (bank 4) |
| ピン 129 | I/O — User I/O pin (bank 4) |
| ピン 130 | I/O — User I/O pin (bank 4) |
| ピン 131 | GND — Ground |
| ピン 132 | I/O — User I/O pin (bank 1) |
| ピン 133 | I/O — User I/O pin (bank 1) |
| ピン 134 | I/O — User I/O pin (bank 1) |
| ピン 135 | I/O — User I/O pin (bank 1) |
| ピン 136 | I/O — User I/O pin (bank 1) |
| ピン 137 | I/O — User I/O pin (bank 1) |
| ピン 138 | VCCIO1 — I/O supply voltage bank 1 |
| ピン 139 | I/O — User I/O pin (bank 1) |
| ピン 140 | I/O — User I/O pin (bank 1) |
| ピン 141 | I/O — User I/O pin (bank 1) |
| ピン 142 | I/O — User I/O pin (bank 1) |
| ピン 143 | I/O — User I/O pin (bank 1) |
| ピン 144 | I/O — User I/O pin (bank 1) |
主な用途
EPM570T144C4 の用途: 7 件s: Bus Bridging and Protocol Translation, Power-On Sequencing and Reset Distribution, I/O Expansion via Serial-to-Parallel Conversion, Glue Logic Replacement for Discrete 74-Series, LED Matrix and Display Driver Controller, Motor Control PWM and Quadrature Decoder, Industrial Communication Gateway (RS-232/RS-485/CAN to UART/SPI).
Bus Bridging and Protocol Translation
The EPM570T144C4 is widely used as a bus-bridging CPLD between legacy microcontrollers (e.g., 8051, PIC) and modern peripherals with mismatched voltage or interface standards. With MultiVolt I/O supporting 1.5/1.8/2.5/3.3 V and 116 user I/Os in the 144-pin TQFP, the device can directly interface two voltage domains without external level shifters. The 5.4 ns pin-to-pin propagation delay handles synchronous interfaces up to ~185 MHz, while the deterministic timing guarantees sub-ns jitter on asynchronous handshakes such as SPI, I2C, and parallel SRAM. Designers typically implement custom state machines in Verilog/VHDL, then synthesize via Quartus II for the JTAG-programmable flash configuration. Recommended companion parts: external SRAM (CY7C1011), SPI Flash (W25Q64), and a 3.3 V LDO for VCCIO.
おすすめ
Power-On Sequencing and Reset Distribution
The EPM570T144C4 excels at multi-rail power-on sequencing in FPGA-based systems, ASIC reference designs, and industrial controllers requiring strict rail-ordering. The 116 I/Os are sufficient to drive dozens of enable and reset lines for downstream regulators, ASICs, and FPGAs. With 5.4 ns tPD and on-chip flash configuration, the CPLD wakes up in <1 ms and starts sequencing rails deterministically - far faster than a microcontroller-based sequencer that must boot from external memory. Engineers commonly combine it with a TPS7A4701 LDO per rail, a TPS3808G33 supervisor for input monitoring, and an external EEPROM for sequence parameters. The non-volatile UFM block (8 Kbits) stores calibration and timing parameters without external storage. Operating temperature range 0C to +85C covers most industrial enclosures.
おすすめ
I/O Expansion via Serial-to-Parallel Conversion
When a microcontroller or FPGA lacks sufficient GPIO, the EPM570T144C4 acts as an I/O expander converting a 4-wire SPI interface to 100+ GPIO with programmable direction, pull-up, and interrupt-on-change. The 570 logic elements support up to 440 macrocells of combinational and registered logic - ample for debounce, edge detect, and PWM generation per pin. The 5.4 ns tPD enables SPI-to-parallel conversion at >50 MHz SCK rates, while the MultiVolt I/O allows the CPLD to drive 1.8 V, 2.5 V, or 3.3 V loads from the same device. JTAG ISP allows field firmware updates to change pin function assignments without board rework. Companion parts: STM32F103 host MCU, SN74HC595 shift registers (for additional expansion beyond 116 I/Os), and CH340G USB-SPI bridge for programming.
おすすめ
Glue Logic Replacement for Discrete 74-Series
The EPM570T144C4 replaces dozens of discrete 74HC/74AHC/74LVTH logic packages (latches, decoders, muxes, gates) with a single programmable device, reducing board area and BOM cost in legacy designs being modernized. A typical 570-LE design can absorb the function of 20-40 discrete SSI/MSI packages that would otherwise occupy hundreds of square millimeters of board space. The 5.4 ns tPD matches or exceeds 74HC04 (~7 ns) and 74AHC (~5 ns) performance. Designers can also add incremental features (status LEDs, test points, fault injection) without modifying the board. The 144-pin TQFP is a proven industrial footprint for reflow assembly. Quartus II schematic capture supports direct symbol import from legacy 74-series libraries for rapid migration.
おすすめ
LED Matrix and Display Driver Controller
The EPM570T144C4 drives LED matrix displays (8x8 RGB up to 16x16 monochrome) with hardware-based multiplexing, freeing the host processor from real-time refresh duties. With 116 I/Os and 5.4 ns tPD, the device can drive row/column drivers with zero CPU overhead using internal counters, comparators, and PWM modulators implemented in the 570 logic elements. Multi-row persistence-of-vision (POV) designs benefit from the deterministic timing. The 8 Kbit UFM stores gamma correction tables and frame buffers for stand-alone animation playback. Operating from 0C to +85C covers commercial signage and indoor industrial displays. Companion parts: TLC5941 16-channel LED driver, STP16DP05 16-bit constant-current sink, and STM32 host for image loading.
おすすめ
Motor Control PWM and Quadrature Decoder
The EPM570T144C4 implements multi-axis motor control peripherals in industrial servo and stepper systems - quadrature decoders, PWM generators, direction control, and fault handling - offloading the real-time loop from the main MCU. The 5.4 ns tPD enables 200 kHz+ PWM frequencies with center-aligned or edge-aligned modes and dead-time insertion, while 116 I/Os can simultaneously monitor 4-6 encoder inputs and drive 12-24 FET half-bridges via gate drivers. Hardware fault inputs (overcurrent, overtemperature) can immediately tristate outputs in <10 ns via internal routing, providing safety-critical response time faster than any software interrupt. Operating up to +85C is sufficient for enclosed motor cabinets. Companion parts: DRV8301 three-phase gate driver, IRFS4010 power MOSFETs, and AS5048A magnetic encoder.
おすすめ
Industrial Communication Gateway (RS-232/RS-485/CAN to UART/SPI)
The EPM570T144C4 acts as a hardware protocol converter between legacy industrial fieldbuses (RS-232, RS-485, CAN) and modern serial interfaces (SPI, I2C, UART) in PLCs and industrial gateways. The 570 logic elements handle the entire UART stack (bit timing, parity, FIFO buffering) for 4-8 independent channels without CPU intervention. 116 I/Os connect to multiple transceiver ICs (MAX485, SN65HVD230, MAX232) in parallel. The 5.4 ns tPD and 304 MHz internal frequency handle bit rates up to 1 Mbaud with zero software overhead. The 0C to +85C range covers factory-floor environments. JTAG ISP enables in-field protocol stack updates for new device integration. Companion parts: MAX485 RS-485 transceiver, SN65HVD230 CAN transceiver, STM32F407 host MCU.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: EPM570T144C4 — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | EPM570T144C5N | EPM570T144C3N | EPM570T144A5N | EPM570T144-5 | EPM570T144C4N |
|---|---|---|---|---|---|---|
| Brand | Intel | Intel | Intel | Intel | Intel | Intel |
| Package | 144-pin TQFP (20x20 mm, 0.5 mm pitch) | 144-pin TQFP - same | 144-pin TQFP - same | 144-pin TQFP - same | 144-pin TQFP - same | 144-pin TQFP - same |
| Logic Elements | 570 | 570 | 570 | 570 | 570 | 570 |
| Equivalent Macrocells | 440 | 440 | 440 | 440 | 440 | 440 |
| Maximum User I/Os | 116 | 116 | 116 | 116 | 116 | 116 |
| Speed Grade Suffix | C4 | C5 | C3 | A5 (lower power) | -5 (legacy C5) | C4N (lead-free) |
| Operating Temperature | 0C to +85C (commercial) | 0C to +85C | 0C to +85C | 0C to +85C | 0C to +85C | 0C to +85C |
| Approx. Unit Price (qty 1) | $37.66 | $40-45 (faster grade) | $35-40 | $40-45 (lower power) | $40-45 | $38-42 |
主な差別化要因
- Non-volatile flash configuration - instant-on in <1 ms （vs EPM570T144C5N)
- MultiVolt I/O supports 1.5 V to 3.3 V mixed-voltage design on a single device （vs EPM570T144A5N)
- Vertical migration in same 144-pin TQFP package across EPM570 / EPM1270 / EPM2210 （vs EPM570T144-5 (legacy -5 grade))
- On-chip 8 Kbit UFM eliminates external EEPROM in many designs （vs Discrete 74-series logic packages)
設計ノート
The EPM570T144C4 requires two separate supply rails: VCCINT (1.8 V core) and VCCIO (1.5/1.8/2.5/3.3 V I/O). All four VCCINT pins (21, 61, 91, 121) and all four VCCIO pins (one per bank: 8, 37, 77, 108, 138) must be decoupled with 0.1 uF ceramic capacitors placed within 5 mm of each pin. Add a 10 uF bulk capacitor near the VCCINT pins. Power-on sequence is not critical - both rails can ramp simultaneously - but VCCINT must reach 0.6 V before VCCIO to prevent latch-up during slow power ramps.
The 144-pin TQFP package has a typical theta_JA of approximately 28 C/W (still air, JEDEC 4-layer PCB). At maximum operating frequency (304 MHz) and 90% logic utilization, the device dissipates approximately 200 mW, yielding a 6C temperature rise above ambient. This is well within the 0C to +85C operating range without a heatsink. For extended industrial temperature operation, ensure ambient temperature does not exceed +79C at full speed and full utilization. The exposed thermal pad is not present on the TQFP package (unlike the BGA variants), so all heat dissipation occurs through the perimeter leads.
Route JTAG signals (TCK, TMS, TDI, TDO on pins 47, 46, 45, 48) as a single chain with no stubs. Place a 10 kohm pull-up on TCK and TMS, and a 10 kohm pull-up on TDI to keep the JTAG state machine in a known state at power-up. Connect TDO to the next device's TDI in chain mode (unused in single-device configuration). Reserve a 4-pin 0.1 inch header footprint for the Altera USB-Blaster JTAG connection - this enables in-system programming without removing the board from the chassis. Keep JTAG traces short (<50 mm total) and shielded from switching signals.
Common pitfalls with the EPM570T144C4 include: (1) Forgetting that the device has NO 5 V tolerance - 5 V signals will damage the I/O unless external level shifters are used; (2) Assigning too many pins to bank 1 without verifying VCCIO1 can supply the required current (each VCCIO bank has a maximum of approximately 100 mA for the entire bank); (3) Exceeding the UFM endurance spec of 1000 erase/program cycles if using the flash memory for high-update-rate data logging - the UFM is intended for parameter storage, not data logging; (4) Forgetting to specify the I/O standard (LVCMOS/LVTTL) for each pin in the Quartus pin planner - unassigned I/O defaults to weak pull-up which may cause unintended current draw.
コンプライアンス情報
Standard EPM570T144C4 uses SnPb terminal finish (non-lead-free); use EPM570T144C4N for fully lead-free RoHS assembly. Not AEC-Q100 qualified - MAX II CPLDs are not marketed for automotive safety-critical applications.
