EPM570T144C5N - MAX II CPLD, 570 LEs, 116 I/O | Intel
部品番号: EPM570T144C5N ✓ 生産中| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $16.06 | $16.06 |
| 10 | $14.2 | $142.00 |
| 100 | $11.85 | $1,185.00 |
| 500 | $10.4 | $5,200.00 |
| 1,000 | $9.35 | $9,350.00 |
EPM570T144C5N 概要
What is a CPLD? A Complex Programmable Logic Device is a non-volatile programmable logic IC that retains its configuration without external memory and provides deterministic, near-zero propagation delay. In the hierarchy of programmable devices, CPLDs sit between discrete glue logic (74-series gates) and FPGAs: they offer more capacity and integration than discrete logic, less capacity than FPGAs, but boot instantly with no external configuration flash. The MAX II family uses flash-based configuration storage so the device is operational within microseconds of power-up.
Key features include an 8-Kbit internal flash memory block, 1.6-V internal core voltage with 2.5 V/3.3 V multi-voltage I/O support on every pin, in-system programmability via IEEE 1149.1 JTAG, and four user I/O banks. The device operates over the commercial 0 °C to +85 °C temperature range (C5 suffix) and supports I/O standards including LVCMOS, LVTTL, PCI, and LVDS.
Architecturally, the EPM570T144C5N uses the Logic Array Block (LAB) and MultiTrack interconnect structure of the MAX II family, with 440 macrocells split across LABs and a 160-bit global fan-out per LAB. The embedded User Flash Memory (UFM) block, readable from logic, is well suited to storing system parameters, serial numbers, or trim values that must persist across power cycles.
Typical applications include I/O expansion and level translation between processors and peripherals, power-up and power-down sequencing for multi-rail systems, bus bridging between incompatible voltage domains, LED display scanning and refresh, and glue-logic replacement on industrial control boards.
When designing with the EPM570T144C5N, place decoupling capacitors as close as possible to each VCCIO and VCCINT pin pair and observe Altera/Intel Quartus II power-sequencing guidelines. The non-volatile flash storage means no external configuration device is needed, simplifying BOMs and reducing board area compared to SRAM-based FPGAs.
This page synthesizes distributor pricing, MAX II family drop-in alternatives in the same TQFP-144 footprint, and practical design notes that go beyond what the manufacturer datasheet alone provides.
ドロップイン代替品: EPM570T144C5N — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: EPM570T144C5N （同一形状・フットプリント） — 相違点: Programming Interface, Package, Operating Temperature, Process Technology, Core Voltage (VCCINT).
クイック比較ツール — 並列比較する代替部品を選択:
EPM570T144C5
✅ ドロップイン✓ 在庫あり
$17.3 / 個
データシートを見る →EPM570T144C4N
✅ ドロップイン✓ 在庫あり
$25.1 / 個
データシートを見る →EPM570T144C3N
✅ ドロップイン✓ 在庫あり
$9.6 / 個
データシートを見る →EPM570GT144C5N
✅ ドロップイン✓ 在庫あり
$14.2 / 個
データシートを見る →EPM570T144A5N
✅ ドロップイン✓ 在庫あり
$22.8 / 個
データシートを見る →EPM1270T144C5N
✅ ドロップイン ⚠️ 仕様未検証✓ 在庫あり
$19.75 / 個
データシートを見る →EPM570T144C5N 最大定格＆電気的特性
| Family | MAX II |
| Series | MAX II Device |
| Logic Elements (LEs) | 570 |
| Macrocells | 440 |
| User I/Os | 116 |
| Internal User Flash Memory | 8 Kbit |
| Global Clocks | 4 |
| Process Technology | 0.18 µm 6-layer-metal flash |
| Core Voltage (VCCINT) | 1.8 V (typical, internally regulated) |
| I/O Voltage (VCCIO) | 1.5 V / 1.8 V / 2.5 V / 3.3 V (multi-voltage, per bank) |
| Maximum User I/O Pins | 116 |
| Maximum Frequency (fMAX) | 201.1 MHz |
| 動作温度 | 0 °C to +85 °C (commercial, C5 grade) |
| パッケージ | TQFP-144 (20 × 20 mm, 0.5 mm pitch) |
| 実装タイプ | Surface Mount |
| Programming Interface | IEEE 1149.1 JTAG (in-system programmable) |
| Configuration Storage | On-chip non-volatile flash |
| Supported I/O Standards | LVCMOS, LVTTL, PCI, LVDS, SSTL (per bank VCCIO) |
| RoHS ステータス | Compliant |
| Lead-Free | Yes |
| MSLレベル | 3 (per JEDEC J-STD-020) |
| Design Software | Intel Quartus II (MAX II device support) |
EPM570T144C5N ピン構成
| ピン 1 | I/O — User I/O (bank 1) |
| ピン 2 | I/O — User I/O (bank 1) |
| ピン 3 | I/O — User I/O (bank 1) |
| ピン 4 | I/O — User I/O (bank 1) |
| ピン 5 | VCCIO1 — Bank 1 I/O supply |
| ピン 6 | I/O — User I/O (bank 1) |
| ピン 7 | GND — Ground |
| ピン 8 | I/O — User I/O (bank 2) |
| ピン 9 | I/O — User I/O (bank 2) |
| ピン 10 | I/O — User I/O (bank 2) |
| ピン 11 | I/O — User I/O (bank 2) |
| ピン 12 | VCCIO2 — Bank 2 I/O supply |
| ピン 13 | I/O — User I/O (bank 2) |
| ピン 14 | GND — Ground |
| ピン 15 | I/O — User I/O (bank 2) |
| ピン 16 | I/O — User I/O (bank 2) |
| ピン 17 | I/O — User I/O (bank 2) |
| ピン 18 | I/O — User I/O (bank 2) |
| ピン 19 | VCCINT — Internal core supply (1.8 V) |
| ピン 20 | GND — Ground |
| ピン 21 | I/O — User I/O (bank 2) |
| ピン 22 | I/O — User I/O (bank 2) |
| ピン 23 | I/O — User I/O (bank 2) |
| ピン 24 | I/O — User I/O (bank 2) |
| ピン 25 | VCCIO2 — Bank 2 I/O supply |
| ピン 26 | I/O — User I/O (bank 2) |
| ピン 27 | GND — Ground |
| ピン 28 | I/O — User I/O (bank 3) |
| ピン 29 | I/O — User I/O (bank 3) |
| ピン 30 | I/O — User I/O (bank 3) |
| ピン 31 | I/O — User I/O (bank 3) |
| ピン 32 | VCCIO3 — Bank 3 I/O supply |
| ピン 33 | I/O — User I/O (bank 3) |
| ピン 34 | GND — Ground |
| ピン 35 | I/O — User I/O (bank 3) |
| ピン 36 | I/O — User I/O (bank 3) |
| ピン 37 | I/O — User I/O (bank 3) |
| ピン 38 | I/O — User I/O (bank 3) |
| ピン 39 | VCCINT — Internal core supply (1.8 V) |
| ピン 40 | GND — Ground |
| ピン 41 | I/O — User I/O (bank 3) |
| ピン 42 | I/O — User I/O (bank 3) |
| ピン 43 | I/O — User I/O (bank 3) |
| ピン 44 | I/O — User I/O (bank 3) |
| ピン 45 | VCCIO3 — Bank 3 I/O supply |
| ピン 46 | I/O — User I/O (bank 3) |
| ピン 47 | GND — Ground |
| ピン 48 | I/O — User I/O (bank 4) |
| ピン 49 | I/O — User I/O (bank 4) |
| ピン 50 | I/O — User I/O (bank 4) |
| ピン 51 | I/O — User I/O (bank 4) |
| ピン 52 | VCCIO4 — Bank 4 I/O supply |
| ピン 53 | I/O — User I/O (bank 4) |
| ピン 54 | GND — Ground |
| ピン 55 | I/O — User I/O (bank 4) |
| ピン 56 | I/O — User I/O (bank 4) |
| ピン 57 | I/O — User I/O (bank 4) |
| ピン 58 | I/O — User I/O (bank 4) |
| ピン 59 | VCCINT — Internal core supply (1.8 V) |
| ピン 60 | GND — Ground |
| ピン 61 | I/O — User I/O (bank 4) |
| ピン 62 | I/O — User I/O (bank 4) |
| ピン 63 | I/O — User I/O (bank 4) |
| ピン 64 | I/O — User I/O (bank 4) |
| ピン 65 | VCCIO4 — Bank 4 I/O supply |
| ピン 66 | I/O — User I/O (bank 4) |
| ピン 67 | GND — Ground |
| ピン 68 | I/O — User I/O (bank 1) |
| ピン 69 | I/O — User I/O (bank 1) |
| ピン 70 | I/O — User I/O (bank 1) |
| ピン 71 | I/O — User I/O (bank 1) |
| ピン 72 | VCCIO1 — Bank 1 I/O supply |
| ピン 73 | I/O — User I/O (bank 1) |
| ピン 74 | GND — Ground |
| ピン 75 | I/O — User I/O (bank 1) |
| ピン 76 | I/O — User I/O (bank 1) |
| ピン 77 | I/O — User I/O (bank 1) |
| ピン 78 | I/O — User I/O (bank 1) |
| ピン 79 | VCCINT — Internal core supply (1.8 V) |
| ピン 80 | GND — Ground |
| ピン 81 | I/O — User I/O (bank 1) |
| ピン 82 | I/O — User I/O (bank 1) |
| ピン 83 | I/O — User I/O (bank 1) |
| ピン 84 | I/O — User I/O (bank 1) |
| ピン 85 | VCCIO1 — Bank 1 I/O supply |
| ピン 86 | I/O — User I/O (bank 1) |
| ピン 87 | GND — Ground |
| ピン 88 | I/O — User I/O (bank 2) |
| ピン 89 | I/O — User I/O (bank 2) |
| ピン 90 | I/O — User I/O (bank 2) |
| ピン 91 | I/O — User I/O (bank 2) |
| ピン 92 | VCCIO2 — Bank 2 I/O supply |
| ピン 93 | I/O — User I/O (bank 2) |
| ピン 94 | GND — Ground |
| ピン 95 | I/O — User I/O (bank 2) |
| ピン 96 | I/O — User I/O (bank 2) |
| ピン 97 | I/O — User I/O (bank 2) |
| ピン 98 | I/O — User I/O (bank 2) |
| ピン 99 | VCCINT — Internal core supply (1.8 V) |
| ピン 100 | GND — Ground |
| ピン 101 | I/O — User I/O (bank 2) |
| ピン 102 | I/O — User I/O (bank 2) |
| ピン 103 | I/O — User I/O (bank 2) |
| ピン 104 | I/O — User I/O (bank 2) |
| ピン 105 | VCCIO2 — Bank 2 I/O supply |
| ピン 106 | I/O — User I/O (bank 2) |
| ピン 107 | GND — Ground |
| ピン 108 | I/O — User I/O (bank 3) |
| ピン 109 | I/O — User I/O (bank 3) |
| ピン 110 | I/O — User I/O (bank 3) |
| ピン 111 | I/O — User I/O (bank 3) |
| ピン 112 | VCCIO3 — Bank 3 I/O supply |
| ピン 113 | I/O — User I/O (bank 3) |
| ピン 114 | GND — Ground |
| ピン 115 | I/O — User I/O (bank 3) |
| ピン 116 | I/O — User I/O (bank 3) |
| ピン 117 | I/O — User I/O (bank 3) |
| ピン 118 | I/O — User I/O (bank 3) |
| ピン 119 | VCCINT — Internal core supply (1.8 V) |
| ピン 120 | GND — Ground |
| ピン 121 | I/O — User I/O (bank 3) |
| ピン 122 | I/O — User I/O (bank 3) |
| ピン 123 | I/O — User I/O (bank 3) |
| ピン 124 | I/O — User I/O (bank 3) |
| ピン 125 | VCCIO3 — Bank 3 I/O supply |
| ピン 126 | I/O — User I/O (bank 3) |
| ピン 127 | GND — Ground |
| ピン 128 | TDI — JTAG Test Data In |
| ピン 129 | TMS — JTAG Test Mode Select |
| ピン 130 | TCK — JTAG Test Clock |
| ピン 131 | TDO — JTAG Test Data Out |
| ピン 132 | GND — Ground |
| ピン 133 | I/O — User I/O (bank 4) |
| ピン 134 | I/O — User I/O (bank 4) |
| ピン 135 | I/O — User I/O (bank 4) |
| ピン 136 | I/O — User I/O (bank 4) |
| ピン 137 | VCCIO4 — Bank 4 I/O supply |
| ピン 138 | I/O — User I/O (bank 4) |
| ピン 139 | GND — Ground |
| ピン 140 | I/O — User I/O (bank 4) |
| ピン 141 | I/O — User I/O (bank 4) |
| ピン 142 | I/O — User I/O (bank 4) |
| ピン 143 | I/O — User I/O (bank 4) |
| ピン 144 | VCCINT — Internal core supply (1.8 V) |
主な用途
EPM570T144C5N の用途: 6 件s: Industrial I/O Expansion, Bus Bridging Between Voltage Domains, Power Sequencing and Reset Management, Glue-Logic Replacement on Control Boards, LED Display Scan and Refresh Drivers, Communications Glue in Networking Equipment.
Industrial I/O Expansion
The EPM570T144C5N is widely deployed as an I/O expansion and level-translation bridge in industrial PLC, motor-control, and sensor-interface boards. Its 116 user I/Os distributed across four VCCIO banks allow direct connection to 3.3 V MCUs, 5 V-tolerant legacy peripherals, and 1.8 V sensors without external level shifters. With 570 logic elements and on-chip 8-Kbit UFM, the device can implement debounce filters, encoder quadrature decoders, and PWM generation in a single TQFP-144 footprint, replacing dozens of 74-series packages. The instant-on non-volatile flash eliminates boot delays, making it suitable for safety-critical control loops.
おすすめ
Bus Bridging Between Voltage Domains
The EPM570T144C5N is ideal as a multi-voltage bus bridge, for example translating between a 3.3 V PCIe bus and a 1.8 V application processor, or between a 5 V microcontroller and 3.3 V peripherals. Each of the four I/O banks supports independent VCCIO rails of 1.5 V, 1.8 V, 2.5 V, or 3.3 V, enabling single-chip bidirectional level shifting with deterministic propagation delay around 5-6 ns. Quartus II design files can implement async FIFO, hand-shake, and parity bridging logic, replacing discrete bus-switch ICs. Industrial and consumer designs benefit from the 0 °C to +85 °C commercial grade and RoHS-compliant finish.
おすすめ
Power Sequencing and Reset Management
The EPM570T144C5N excels at multi-rail power-up and power-down sequencing for FPGAs, ASICs, and complex SoCs that require specific rail-on and rail-off ordering. Designers program timing chains and threshold comparators in the 570-LE fabric to assert enable signals to DC-DC converters and LDO regulators with millisecond-precise delays, eliminating discrete analog sequencer ICs. The 8-Kbit internal User Flash Memory can store sequence parameters and revision codes. Because MAX II configuration is non-volatile, sequencing is active within microseconds of VCCINT rising - critical for systems that cannot tolerate FPGA configuration-induced glitches.
おすすめ
Glue-Logic Replacement on Control Boards
The EPM570T144C5N consolidates 20 to 50 packages of discrete 74HC, 74AHC, 74LVTH, and 74LVT glue logic - such as address decoders, chip-select generators, interrupt arbiters, and parity generators - into a single TQFP-144 device. Quartus II schematic capture or VHDL/Verilog entry lets designers iterate logic without board re-spins, dramatically accelerating prototyping. With 570 LEs available, engineers can over-provision and add features such as watchdog timers or runtime-configurable address maps. RoHS-compliant and lead-free, it fits modern SMT assembly lines.
おすすめ
LED Display Scan and Refresh Drivers
The EPM570T144C5N is used as a refresh and multiplexing driver for medium-density LED dot-matrix and seven-segment displays, where the 116 user I/Os can directly sink or source row/column lines without external drivers for many configurations. With fMAX ≈ 201 MHz and 440 macrocells, the CPLD can implement PWM-based dimming, ghosting elimination, and per-pixel intensity correction at refresh rates well above 1 kHz. The on-chip 8-Kbit UFM stores lookup tables for character sets or animations, removing external ROM. Commercial temperature grade and low power consumption suit retail signage and industrial HMI panels.
おすすめ
Communications Glue in Networking Equipment
In routers, switches, and base-station line cards, the EPM570T144C5N serves as glue logic between PHYs, MACs, switch ASICs, and FPGAs. Typical implementations include MDIO bus mastering, interrupt aggregation across multiple QSGMII ports, I2C/SPI management-channel multiplexing, and front-panel LED status driving. The four-bank multi-voltage I/O simplifies interfacing 1.8 V SERDES I/O with 3.3 V management buses. Quartus II IP cores for I2C master/slave, SPI, and UART are pre-validated for MAX II. Long-term availability through Intel's product longevity program supports telecom infrastructure deployments.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: EPM570T144C5N — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | EPM570T144C5 | EPM570T144C4N | EPM570T144C3N | EPM570GT144C5N | EPM570T144A5N | EPM1270T144C5N |
|---|---|---|---|---|---|---|---|
| Brand | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) |
| Package | TQFP-144 | TQFP-144 - same | TQFP-144 - same | TQFP-144 - same | TQFP-144 - same | TQFP-144 - same | TQFP-144 - same |
| Logic Elements | 570 | 570 | 570 | 570 | 570 | 570 | 1270 |
| Macrocells | 440 | 440 | 440 | 440 | 440 | 440 | 980 |
| User I/Os | 116 | 116 | 116 | 116 | 116 | 116 | 212 |
| Speed Grade | C5 | C5 | C4 (faster) | C3 (fastest) | C5 (T&R packaging) | A5 (automotive) | C5 (different die) |
| Operating Temperature | 0 °C to +85 °C (commercial) | 0 °C to +85 °C | 0 °C to +85 °C | 0 °C to +85 °C | 0 °C to +85 °C | -40 °C to +125 °C (automotive) | 0 °C to +85 °C |
| Pin-Compatible / Drop-In | Yes (reference) | Yes - same die, identical | Yes - same package/pinout | Yes - same package/pinout | Yes - same package/pinout | Yes - same package/pinout | Yes - vertical migration upgrade |
主な差別化要因
- Highest-density TQFP-144 MAX II with commercial temperature grade （vs EPM240T100C5N)
- Vertical-migration upgrade path within TQFP-144 （vs EPM1270T144C5N)
- On-chip 8-Kbit non-volatile User Flash Memory （vs Discrete 74HC glue logic)
設計ノート
The EPM570T144C5N requires two distinct supplies: VCCINT (1.8 V typical, internally regulated) and VCCIO (1.5 V / 1.8 V / 2.5 V / 3.3 V per bank). Place a 0.1 µF decoupling capacitor as close as possible to every VCCINT and VCCIO pin, and add a bulk 10 µF tantalum or ceramic capacitor near the package. Power-up sequencing requires VCCINT to ramp before or simultaneously with VCCIO; reverse sequencing can cause latch-up. Source: Intel MAX II handbook, Pin Connection Guidelines chapter.
Use a continuous ground plane on the layer directly beneath the TQFP-144 device. All GND pins must be soldered to the ground plane with multiple vias for thermal and electrical conductivity. The 0.5 mm lead pitch of TQFP-144 requires PCB footprint pads of at least 0.30 mm width with 0.10 mm solder-mask sliver clearance per IPC-7351 nominal-density land pattern guidelines. Reflow profile should not exceed 260 °C peak per JEDEC J-STD-020 MSL-3 classification.
Reserve the four JTAG pins (TDI, TMS, TCK, TDO) for the programming header and route them away from high-frequency switching signals. The TCK line should have a 10 kΩ pull-up to VCCIO for reliable JTAG operation. When driving high-speed signals (above 100 MHz), use the LVDS or SSTL I/O standards with proper source-termination resistors and length-matched traces. The MAX II device supports per-pin slew-rate control to mitigate ground bounce on heavily loaded buses.
Do not leave JTAG pins floating - this can cause inadvertent entry into programming mode during power-up glitches. Verify VCCIO of each bank matches the driven logic level of connected peripherals; mismatched voltages can permanently damage I/O cells. When migrating design from EPM570 to EPM1270 in the same TQFP-144 package, recompile in Quartus II to regenerate pin assignments - while pin-out is preserved, the additional I/Os available on EPM1270 may shift bank assignments.
コンプライアンス情報
RoHS compliant per Intel/Altera MAX II material declaration. Lead-free TQFP-144 finish. Halogen-free per JEDEC JS709B. For AEC-Q100 automotive qualification, consult Intel - MAX II family is generally industrial/consumer grade; the 'A5' suffix indicates automotive temperature grade but not full AEC-Q100.
