EPM570T144C4 - 570 LEs, 116 I/O, 3.3V MAX II CPLD | Intel
MPN: EPM570T144C4 β Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $37.66 | $37.66 |
| 10 | $32.5 | $325.00 |
| 100 | $26.8 | $2,680.00 |
| 500 | $22.45 | $11,225.00 |
| 1,000 | $19.2 | $19,200.00 |
Drop-in alternatives for EPM570T144C4 β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
EPM570T144C5N
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$9.35 / Unit
View Datasheet βEPM570T144C3N
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View Datasheet βEPM570T144A5N
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$22.8 / Unit
View Datasheet βEPM570T144-5
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View Datasheet βEPM570T144C4N
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$25.1 / Unit
View Datasheet βEPM570T144C4 Maximum Ratings & Electrical Characteristics
| Family | MAX II |
| Logic Elements (LEs) | 570 |
| Equivalent Macrocells | 440 |
| Maximum User I/Os | 116 |
| User Flash Memory (UFM) | 8 Kbits |
| Propagation Delay (tPD) | 5.4 ns (fastest speed grade C4) |
| Maximum Internal Frequency | 304 MHz |
| Core Voltage (VCCINT) | 1.8 V (internal) |
| I/O Voltage (VCCIO) | 1.5 V / 1.8 V / 2.5 V / 3.3 V (MultiVolt) |
| Operating Temperature | 0C to +85C (commercial extended) |
| Package | 144-pin TQFP (20 mm x 20 mm, 0.5 mm pitch) |
| Mounting Type | Surface Mount |
| MSL Level | 3 (168 hours) |
| RoHS Status | Compliant |
| Configuration Memory | On-chip flash (non-volatile, instant-on) |
| Programming Interface | JTAG (IEEE 1149.1) - ISP |
EPM570T144C4 Pin Configuration
| Pin 1 | I/O β User I/O pin (bank 1) |
| Pin 2 | I/O β User I/O pin (bank 1) |
| Pin 3 | I/O β User I/O pin (bank 1) |
| Pin 4 | I/O β User I/O pin (bank 1) |
| Pin 5 | I/O β User I/O pin (bank 1) |
| Pin 6 | I/O β User I/O pin (bank 1) |
| Pin 7 | I/O β User I/O pin (bank 1) |
| Pin 8 | VCCIO1 β I/O supply voltage bank 1 |
| Pin 9 | I/O β User I/O pin (bank 1) |
| Pin 10 | I/O β User I/O pin (bank 1) |
| Pin 11 | GND β Ground |
| Pin 12 | I/O β User I/O pin (bank 1) |
| Pin 13 | I/O β User I/O pin (bank 1) |
| Pin 14 | I/O β User I/O pin (bank 1) |
| Pin 15 | I/O β User I/O pin (bank 1) |
| Pin 16 | I/O β User I/O pin (bank 1) |
| Pin 17 | I/O β User I/O pin (bank 1) |
| Pin 18 | I/O β User I/O pin (bank 1) |
| Pin 19 | I/O β User I/O pin (bank 1) |
| Pin 20 | I/O β User I/O pin (bank 1) |
| Pin 21 | VCCINT β Core supply voltage (1.8 V) |
| Pin 22 | I/O β User I/O pin (bank 1) |
| Pin 23 | I/O β User I/O pin (bank 1) |
| Pin 24 | I/O β User I/O pin (bank 1) |
| Pin 25 | I/O β User I/O pin (bank 1) |
| Pin 26 | I/O β User I/O pin (bank 1) |
| Pin 27 | I/O β User I/O pin (bank 1) |
| Pin 28 | I/O β User I/O pin (bank 1) |
| Pin 29 | I/O β User I/O pin (bank 1) |
| Pin 30 | GND β Ground |
| Pin 31 | I/O β User I/O pin (bank 2) |
| Pin 32 | I/O β User I/O pin (bank 2) |
| Pin 33 | I/O β User I/O pin (bank 2) |
| Pin 34 | I/O β User I/O pin (bank 2) |
| Pin 35 | I/O β User I/O pin (bank 2) |
| Pin 36 | I/O β User I/O pin (bank 2) |
| Pin 37 | VCCIO2 β I/O supply voltage bank 2 |
| Pin 38 | I/O β User I/O pin (bank 2) |
| Pin 39 | I/O β User I/O pin (bank 2) |
| Pin 40 | I/O β User I/O pin (bank 2) |
| Pin 41 | I/O β User I/O pin (bank 2) |
| Pin 42 | I/O β User I/O pin (bank 2) |
| Pin 43 | I/O β User I/O pin (bank 2) |
| Pin 44 | I/O β User I/O pin (bank 2) |
| Pin 45 | TDI β JTAG Test Data In |
| Pin 46 | TMS β JTAG Test Mode Select |
| Pin 47 | TCK β JTAG Test Clock |
| Pin 48 | TDO β JTAG Test Data Out |
| Pin 49 | I/O β User I/O pin (bank 2) |
| Pin 50 | GND β Ground |
| Pin 51 | I/O β User I/O pin (bank 2) |
| Pin 52 | I/O β User I/O pin (bank 2) |
| Pin 53 | I/O β User I/O pin (bank 2) |
| Pin 54 | I/O β User I/O pin (bank 2) |
| Pin 55 | I/O β User I/O pin (bank 2) |
| Pin 56 | I/O β User I/O pin (bank 2) |
| Pin 57 | I/O β User I/O pin (bank 2) |
| Pin 58 | I/O β User I/O pin (bank 2) |
| Pin 59 | I/O β User I/O pin (bank 2) |
| Pin 60 | I/O β User I/O pin (bank 2) |
| Pin 61 | VCCINT β Core supply voltage (1.8 V) |
| Pin 62 | I/O β User I/O pin (bank 2) |
| Pin 63 | I/O β User I/O pin (bank 2) |
| Pin 64 | I/O β User I/O pin (bank 2) |
| Pin 65 | I/O β User I/O pin (bank 2) |
| Pin 66 | I/O β User I/O pin (bank 2) |
| Pin 67 | I/O β User I/O pin (bank 2) |
| Pin 68 | I/O β User I/O pin (bank 2) |
| Pin 69 | I/O β User I/O pin (bank 2) |
| Pin 70 | GND β Ground |
| Pin 71 | I/O β User I/O pin (bank 3) |
| Pin 72 | I/O β User I/O pin (bank 3) |
| Pin 73 | I/O β User I/O pin (bank 3) |
| Pin 74 | I/O β User I/O pin (bank 3) |
| Pin 75 | I/O β User I/O pin (bank 3) |
| Pin 76 | I/O β User I/O pin (bank 3) |
| Pin 77 | VCCIO3 β I/O supply voltage bank 3 |
| Pin 78 | I/O β User I/O pin (bank 3) |
| Pin 79 | I/O β User I/O pin (bank 3) |
| Pin 80 | I/O β User I/O pin (bank 3) |
| Pin 81 | I/O β User I/O pin (bank 3) |
| Pin 82 | I/O β User I/O pin (bank 3) |
| Pin 83 | I/O β User I/O pin (bank 3) |
| Pin 84 | I/O β User I/O pin (bank 3) |
| Pin 85 | I/O β User I/O pin (bank 3) |
| Pin 86 | I/O β User I/O pin (bank 3) |
| Pin 87 | I/O β User I/O pin (bank 3) |
| Pin 88 | I/O β User I/O pin (bank 3) |
| Pin 89 | I/O β User I/O pin (bank 3) |
| Pin 90 | I/O β User I/O pin (bank 3) |
| Pin 91 | VCCINT β Core supply voltage (1.8 V) |
| Pin 92 | I/O β User I/O pin (bank 3) |
| Pin 93 | I/O β User I/O pin (bank 3) |
| Pin 94 | I/O β User I/O pin (bank 3) |
| Pin 95 | I/O β User I/O pin (bank 3) |
| Pin 96 | I/O β User I/O pin (bank 3) |
| Pin 97 | I/O β User I/O pin (bank 3) |
| Pin 98 | I/O β User I/O pin (bank 3) |
| Pin 99 | I/O β User I/O pin (bank 3) |
| Pin 100 | I/O β User I/O pin (bank 3) |
| Pin 101 | GND β Ground |
| Pin 102 | I/O β User I/O pin (bank 4) |
| Pin 103 | I/O β User I/O pin (bank 4) |
| Pin 104 | I/O β User I/O pin (bank 4) |
| Pin 105 | I/O β User I/O pin (bank 4) |
| Pin 106 | I/O β User I/O pin (bank 4) |
| Pin 107 | I/O β User I/O pin (bank 4) |
| Pin 108 | VCCIO4 β I/O supply voltage bank 4 |
| Pin 109 | I/O β User I/O pin (bank 4) |
| Pin 110 | I/O β User I/O pin (bank 4) |
| Pin 111 | I/O β User I/O pin (bank 4) |
| Pin 112 | I/O β User I/O pin (bank 4) |
| Pin 113 | I/O β User I/O pin (bank 4) |
| Pin 114 | I/O β User I/O pin (bank 4) |
| Pin 115 | I/O β User I/O pin (bank 4) |
| Pin 116 | I/O β User I/O pin (bank 4) |
| Pin 117 | I/O β User I/O pin (bank 4) |
| Pin 118 | I/O β User I/O pin (bank 4) |
| Pin 119 | I/O β User I/O pin (bank 4) |
| Pin 120 | I/O β User I/O pin (bank 4) |
| Pin 121 | VCCINT β Core supply voltage (1.8 V) |
| Pin 122 | I/O β User I/O pin (bank 4) |
| Pin 123 | I/O β User I/O pin (bank 4) |
| Pin 124 | I/O β User I/O pin (bank 4) |
| Pin 125 | I/O β User I/O pin (bank 4) |
| Pin 126 | I/O β User I/O pin (bank 4) |
| Pin 127 | I/O β User I/O pin (bank 4) |
| Pin 128 | I/O β User I/O pin (bank 4) |
| Pin 129 | I/O β User I/O pin (bank 4) |
| Pin 130 | I/O β User I/O pin (bank 4) |
| Pin 131 | GND β Ground |
| Pin 132 | I/O β User I/O pin (bank 1) |
| Pin 133 | I/O β User I/O pin (bank 1) |
| Pin 134 | I/O β User I/O pin (bank 1) |
| Pin 135 | I/O β User I/O pin (bank 1) |
| Pin 136 | I/O β User I/O pin (bank 1) |
| Pin 137 | I/O β User I/O pin (bank 1) |
| Pin 138 | VCCIO1 β I/O supply voltage bank 1 |
| Pin 139 | I/O β User I/O pin (bank 1) |
| Pin 140 | I/O β User I/O pin (bank 1) |
| Pin 141 | I/O β User I/O pin (bank 1) |
| Pin 142 | I/O β User I/O pin (bank 1) |
| Pin 143 | I/O β User I/O pin (bank 1) |
| Pin 144 | I/O β User I/O pin (bank 1) |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM570T144C4 is suitable for 7 applications: Bus Bridging and Protocol Translation, Power-On Sequencing and Reset Distribution, I/O Expansion via Serial-to-Parallel Conversion, Glue Logic Replacement for Discrete 74-Series, LED Matrix and Display Driver Controller, Motor Control PWM and Quadrature Decoder, Industrial Communication Gateway (RS-232/RS-485/CAN to UART/SPI).
Bus Bridging and Protocol Translation
The EPM570T144C4 is widely used as a bus-bridging CPLD between legacy microcontrollers (e.g., 8051, PIC) and modern peripherals with mismatched voltage or interface standards. With MultiVolt I/O supporting 1.5/1.8/2.5/3.3 V and 116 user I/Os in the 144-pin TQFP, the device can directly interface two voltage domains without external level shifters. The 5.4 ns pin-to-pin propagation delay handles synchronous interfaces up to ~185 MHz, while the deterministic timing guarantees sub-ns jitter on asynchronous handshakes such as SPI, I2C, and parallel SRAM. Designers typically implement custom state machines in Verilog/VHDL, then synthesize via Quartus II for the JTAG-programmable flash configuration. Recommended companion parts: external SRAM (CY7C1011), SPI Flash (W25Q64), and a 3.3 V LDO for VCCIO.
Recommended
Power-On Sequencing and Reset Distribution
The EPM570T144C4 excels at multi-rail power-on sequencing in FPGA-based systems, ASIC reference designs, and industrial controllers requiring strict rail-ordering. The 116 I/Os are sufficient to drive dozens of enable and reset lines for downstream regulators, ASICs, and FPGAs. With 5.4 ns tPD and on-chip flash configuration, the CPLD wakes up in <1 ms and starts sequencing rails deterministically - far faster than a microcontroller-based sequencer that must boot from external memory. Engineers commonly combine it with a TPS7A4701 LDO per rail, a TPS3808G33 supervisor for input monitoring, and an external EEPROM for sequence parameters. The non-volatile UFM block (8 Kbits) stores calibration and timing parameters without external storage. Operating temperature range 0C to +85C covers most industrial enclosures.
Recommended
I/O Expansion via Serial-to-Parallel Conversion
When a microcontroller or FPGA lacks sufficient GPIO, the EPM570T144C4 acts as an I/O expander converting a 4-wire SPI interface to 100+ GPIO with programmable direction, pull-up, and interrupt-on-change. The 570 logic elements support up to 440 macrocells of combinational and registered logic - ample for debounce, edge detect, and PWM generation per pin. The 5.4 ns tPD enables SPI-to-parallel conversion at >50 MHz SCK rates, while the MultiVolt I/O allows the CPLD to drive 1.8 V, 2.5 V, or 3.3 V loads from the same device. JTAG ISP allows field firmware updates to change pin function assignments without board rework. Companion parts: STM32F103 host MCU, SN74HC595 shift registers (for additional expansion beyond 116 I/Os), and CH340G USB-SPI bridge for programming.
Recommended
Glue Logic Replacement for Discrete 74-Series
The EPM570T144C4 replaces dozens of discrete 74HC/74AHC/74LVTH logic packages (latches, decoders, muxes, gates) with a single programmable device, reducing board area and BOM cost in legacy designs being modernized. A typical 570-LE design can absorb the function of 20-40 discrete SSI/MSI packages that would otherwise occupy hundreds of square millimeters of board space. The 5.4 ns tPD matches or exceeds 74HC04 (~7 ns) and 74AHC (~5 ns) performance. Designers can also add incremental features (status LEDs, test points, fault injection) without modifying the board. The 144-pin TQFP is a proven industrial footprint for reflow assembly. Quartus II schematic capture supports direct symbol import from legacy 74-series libraries for rapid migration.
Recommended
LED Matrix and Display Driver Controller
The EPM570T144C4 drives LED matrix displays (8x8 RGB up to 16x16 monochrome) with hardware-based multiplexing, freeing the host processor from real-time refresh duties. With 116 I/Os and 5.4 ns tPD, the device can drive row/column drivers with zero CPU overhead using internal counters, comparators, and PWM modulators implemented in the 570 logic elements. Multi-row persistence-of-vision (POV) designs benefit from the deterministic timing. The 8 Kbit UFM stores gamma correction tables and frame buffers for stand-alone animation playback. Operating from 0C to +85C covers commercial signage and indoor industrial displays. Companion parts: TLC5941 16-channel LED driver, STP16DP05 16-bit constant-current sink, and STM32 host for image loading.
Recommended
Motor Control PWM and Quadrature Decoder
The EPM570T144C4 implements multi-axis motor control peripherals in industrial servo and stepper systems - quadrature decoders, PWM generators, direction control, and fault handling - offloading the real-time loop from the main MCU. The 5.4 ns tPD enables 200 kHz+ PWM frequencies with center-aligned or edge-aligned modes and dead-time insertion, while 116 I/Os can simultaneously monitor 4-6 encoder inputs and drive 12-24 FET half-bridges via gate drivers. Hardware fault inputs (overcurrent, overtemperature) can immediately tristate outputs in <10 ns via internal routing, providing safety-critical response time faster than any software interrupt. Operating up to +85C is sufficient for enclosed motor cabinets. Companion parts: DRV8301 three-phase gate driver, IRFS4010 power MOSFETs, and AS5048A magnetic encoder.
Recommended
Industrial Communication Gateway (RS-232/RS-485/CAN to UART/SPI)
The EPM570T144C4 acts as a hardware protocol converter between legacy industrial fieldbuses (RS-232, RS-485, CAN) and modern serial interfaces (SPI, I2C, UART) in PLCs and industrial gateways. The 570 logic elements handle the entire UART stack (bit timing, parity, FIFO buffering) for 4-8 independent channels without CPU intervention. 116 I/Os connect to multiple transceiver ICs (MAX485, SN65HVD230, MAX232) in parallel. The 5.4 ns tPD and 304 MHz internal frequency handle bit rates up to 1 Mbaud with zero software overhead. The 0C to +85C range covers factory-floor environments. JTAG ISP enables in-field protocol stack updates for new device integration. Companion parts: MAX485 RS-485 transceiver, SN65HVD230 CAN transceiver, STM32F407 host MCU.
Recommended
Recommended Products Summary
Engineering reference data for EPM570T144C4 β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM570T144C5N | EPM570T144C3N | EPM570T144A5N | EPM570T144-5 | EPM570T144C4N |
|---|---|---|---|---|---|---|
| Brand | Intel | Intel | Intel | Intel | Intel | Intel |
| Package | 144-pin TQFP (20x20 mm, 0.5 mm pitch) | 144-pin TQFP - same | 144-pin TQFP - same | 144-pin TQFP - same | 144-pin TQFP - same | 144-pin TQFP - same |
| Logic Elements | 570 | 570 | 570 | 570 | 570 | 570 |
| Equivalent Macrocells | 440 | 440 | 440 | 440 | 440 | 440 |
| Maximum User I/Os | 116 | 116 | 116 | 116 | 116 | 116 |
| Propagation Delay (tPD1) | 5.4 ns | 5.0 ns (~7% faster) | 4.5 ns (~17% faster) | [DATA_NEEDED] | 5.0 ns (-5 grade) | 5.4 ns (identical) |
| Speed Grade Suffix | C4 | C5 | C3 | A5 (lower power) | -5 (legacy C5) | C4N (lead-free) |
| Operating Temperature | 0C to +85C (commercial) | 0C to +85C | 0C to +85C | 0C to +85C | 0C to +85C | 0C to +85C |
| Lead-Free / RoHS | SnPb finish (use C4N for Pb-free) | Yes (lead-free) | Yes (lead-free) | Yes (lead-free) | [DATA_NEEDED] | Yes (lead-free) |
| Approx. Unit Price (qty 1) | $37.66 | $40-45 (faster grade) | $35-40 | $40-45 (lower power) | $40-45 | $38-42 |
Key Differentiators
- Non-volatile flash configuration - instant-on in <1 ms (vs EPM570T144C5N)
- MultiVolt I/O supports 1.5 V to 3.3 V mixed-voltage design on a single device (vs EPM570T144A5N)
- Vertical migration in same 144-pin TQFP package across EPM570 / EPM1270 / EPM2210 (vs EPM570T144-5 (legacy -5 grade))
- On-chip 8 Kbit UFM eliminates external EEPROM in many designs (vs Discrete 74-series logic packages)
Design Notes
The EPM570T144C4 requires two separate supply rails: VCCINT (1.8 V core) and VCCIO (1.5/1.8/2.5/3.3 V I/O). All four VCCINT pins (21, 61, 91, 121) and all four VCCIO pins (one per bank: 8, 37, 77, 108, 138) must be decoupled with 0.1 uF ceramic capacitors placed within 5 mm of each pin. Add a 10 uF bulk capacitor near the VCCINT pins. Power-on sequence is not critical - both rails can ramp simultaneously - but VCCINT must reach 0.6 V before VCCIO to prevent latch-up during slow power ramps.
The 144-pin TQFP package has a typical theta_JA of approximately 28 C/W (still air, JEDEC 4-layer PCB). At maximum operating frequency (304 MHz) and 90% logic utilization, the device dissipates approximately 200 mW, yielding a 6C temperature rise above ambient. This is well within the 0C to +85C operating range without a heatsink. For extended industrial temperature operation, ensure ambient temperature does not exceed +79C at full speed and full utilization. The exposed thermal pad is not present on the TQFP package (unlike the BGA variants), so all heat dissipation occurs through the perimeter leads.
Route JTAG signals (TCK, TMS, TDI, TDO on pins 47, 46, 45, 48) as a single chain with no stubs. Place a 10 kohm pull-up on TCK and TMS, and a 10 kohm pull-up on TDI to keep the JTAG state machine in a known state at power-up. Connect TDO to the next device's TDI in chain mode (unused in single-device configuration). Reserve a 4-pin 0.1 inch header footprint for the Altera USB-Blaster JTAG connection - this enables in-system programming without removing the board from the chassis. Keep JTAG traces short (<50 mm total) and shielded from switching signals.
Common pitfalls with the EPM570T144C4 include: (1) Forgetting that the device has NO 5 V tolerance - 5 V signals will damage the I/O unless external level shifters are used; (2) Assigning too many pins to bank 1 without verifying VCCIO1 can supply the required current (each VCCIO bank has a maximum of approximately 100 mA for the entire bank); (3) Exceeding the UFM endurance spec of 1000 erase/program cycles if using the flash memory for high-update-rate data logging - the UFM is intended for parameter storage, not data logging; (4) Forgetting to specify the I/O standard (LVCMOS/LVTTL) for each pin in the Quartus pin planner - unassigned I/O defaults to weak pull-up which may cause unintended current draw.
Compliance Information
Standard EPM570T144C4 uses SnPb terminal finish (non-lead-free); use EPM570T144C4N for fully lead-free RoHS assembly. Not AEC-Q100 qualified - MAX II CPLDs are not marketed for automotive safety-critical applications.
