EPM570T144C3N - 570 LEs MAX II CPLD, TQFP-144 | Altera/Intel
部品番号: EPM570T144C3N ✓ 生産中| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $15.6 | $15.60 |
| 10 | $14.25 | $142.50 |
| 100 | $12.4 | $1,240.00 |
| 500 | $10.85 | $5,425.00 |
| 1,000 | $9.6 | $9,600.00 |
EPM570T144C3N 概要
A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that combines multiple PAL-like macrocell blocks on a single chip, interconnected by a programmable switch matrix. In the system hierarchy it sits below an FPGA and above a discrete logic array: it is used for glue logic, bus interfacing, power-up sequencing, and small state-machine functions where instant-on (no boot PROM needed), deterministic timing, and high I/O count matter more than raw density. MAX II devices add an 8-Kbit User Flash Memory (UFM) block and MultiVolt I/O, making them suitable for I/O bridging across mixed-voltage rails.
Key features of the EPM570T144C3N include 8 Kbits of embedded UFM, in-system programmability through the standard IEEE 1149.1 JTAG interface, MultiVolt core supporting 3.3V operation, and a Schmitt-trigger input option on every I/O for noisy environments. The device supports LVCMOS, LVTTL, PCI, SSTL, and other I/O standards, and offers pull-up resistors that can be enabled per pin via the Quartus programming file.
Architecturally, the EPM570T144C3N uses a flash-based non-volatile configuration cell so it behaves like an ASIC at power-up - no external boot memory is required and the device is functional within microseconds of VCC ramp. The 5.4 ns pin-to-pin delay and ~300 MHz maximum frequency make it well suited to high-speed decoding, interrupt steering, and register-intensive glue logic on boards containing microprocessors, microcontrollers, or DSPs.
Typical applications include I/O expansion and voltage translation between microcontrollers and peripherals, glue logic in communications infrastructure (routers, switches, base stations), industrial control and factory-automation boards, automotive body and infotainment controllers, and consumer-electronics glue that previously required discrete 74-series logic. It is also a popular choice for prototyping because designs can be rapidly iterated in Altera/Intel Quartus and programmed in-system.
When designing with this part, verify that the Quartus II / Quartus Prime version targeted by the firmware is compatible with the EPM570T144 device family, and budget decoupling capacitance as recommended in the MAX II handbook. The non-volatile flash cell array means retention and endurance limits should be reviewed for production programming volumes.
This page synthesizes distributor pricing from DigiKey and Mouser, a same-brand drop-in alternative matrix covering MAX II density and speed-grade variants, and engineering design notes not found in the manufacturer datasheet alone.
ドロップイン代替品: EPM570T144C3N — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: EPM570T144C3N （同一形状・フットプリント） — 相違点: Programming Interface, Package, Operating Temperature, Process Technology, Maximum User I/O Pins.
クイック比較ツール — 並列比較する代替部品を選択:
EPM570GT144C3N
✅ ドロップイン✓ 在庫あり
$28.95 / 個
データシートを見る →EPM570T144C3
✅ ドロップイン✓ 在庫あり
$27.4 / 個
データシートを見る →EPM570T144-5
✅ ドロップイン✓ 在庫あり
$9.85 / 個
データシートを見る →EPM570T144A5N
✅ ドロップイン✓ 在庫あり
$22.8 / 個
データシートを見る →EPM570T144C5N
✅ ドロップイン✓ 在庫あり
$9.35 / 個
データシートを見る →EPM570GT144C5N
✅ ドロップイン✓ 在庫あり
$14.2 / 個
データシートを見る →EPM570T144C3N 最大定格＆電気的特性
| Family | MAX II |
| Device | EPM570 |
| Logic Elements | 570 |
| Typical Macrocells | 440 |
| User I/Os | 116 |
| User Flash Memory (UFM) | 8 Kbits |
| Propagation Delay (tPD) | 5.4 ns (max) |
| Maximum Frequency (fMAX) | 300 MHz (typ) |
| Core Voltage | 3.3 V |
| 動作温度 | 0C to +85C (commercial) |
| パッケージ | TQFP-144 |
| Process | 0.18 µm, 6-layer-metal flash CMOS |
| Programming Interface | JTAG (IEEE 1149.1), ISP |
| 実装タイプ | Surface Mount |
| RoHS ステータス | Compliant |
EPM570T144C3N ピン構成
| ピン 1 | I/O — General-purpose user I/O bank 1 |
| ピン 2 | I/O — General-purpose user I/O bank 1 |
| ピン 3 | I/O — General-purpose user I/O bank 1 |
| ピン 4 | I/O — General-purpose user I/O bank 1 |
| ピン 5 | I/O — General-purpose user I/O bank 1 |
| ピン 6 | I/O — General-purpose user I/O bank 1 |
| ピン 7 | I/O — General-purpose user I/O bank 1 |
| ピン 8 | I/O — General-purpose user I/O bank 1 |
| ピン 9 | I/O — General-purpose user I/O bank 1 |
| ピン 10 | I/O — General-purpose user I/O bank 1 |
| ピン 11 | I/O — General-purpose user I/O bank 1 |
| ピン 12 | I/O — General-purpose user I/O bank 1 |
| ピン 13 | GND — Ground |
| ピン 14 | I/O — General-purpose user I/O bank 1 |
| ピン 15 | I/O — General-purpose user I/O bank 1 |
| ピン 16 | I/O — General-purpose user I/O bank 1 |
| ピン 17 | I/O — General-purpose user I/O bank 1 |
| ピン 18 | I/O — General-purpose user I/O bank 1 |
| ピン 19 | I/O — General-purpose user I/O bank 1 |
| ピン 20 | I/O — General-purpose user I/O bank 1 |
| ピン 21 | I/O — General-purpose user I/O bank 1 |
| ピン 22 | I/O — General-purpose user I/O bank 1 |
| ピン 23 | I/O — General-purpose user I/O bank 1 |
| ピン 24 | I/O — General-purpose user I/O bank 1 |
| ピン 25 | VCCIO1 — I/O bank 1 supply voltage |
| ピン 26 | I/O — General-purpose user I/O bank 1 |
| ピン 27 | I/O — General-purpose user I/O bank 1 |
| ピン 28 | I/O — General-purpose user I/O bank 1 |
| ピン 29 | I/O — General-purpose user I/O bank 1 |
| ピン 30 | I/O — General-purpose user I/O bank 1 |
| ピン 31 | I/O — General-purpose user I/O bank 1 |
| ピン 32 | I/O — General-purpose user I/O bank 1 |
| ピン 33 | I/O — General-purpose user I/O bank 1 |
| ピン 34 | I/O — General-purpose user I/O bank 1 |
| ピン 35 | I/O — General-purpose user I/O bank 1 |
| ピン 36 | I/O — General-purpose user I/O bank 1 |
| ピン 37 | GND — Ground |
| ピン 38 | I/O — General-purpose user I/O bank 2 |
| ピン 39 | I/O — General-purpose user I/O bank 2 |
| ピン 40 | I/O — General-purpose user I/O bank 2 |
| ピン 41 | I/O — General-purpose user I/O bank 2 |
| ピン 42 | I/O — General-purpose user I/O bank 2 |
| ピン 43 | I/O — General-purpose user I/O bank 2 |
| ピン 44 | I/O — General-purpose user I/O bank 2 |
| ピン 45 | I/O — General-purpose user I/O bank 2 |
| ピン 46 | I/O — General-purpose user I/O bank 2 |
| ピン 47 | I/O — General-purpose user I/O bank 2 |
| ピン 48 | I/O — General-purpose user I/O bank 2 |
| ピン 49 | I/O — General-purpose user I/O bank 2 |
| ピン 50 | VCCIO2 — I/O bank 2 supply voltage |
| ピン 51 | I/O — General-purpose user I/O bank 2 |
| ピン 52 | I/O — General-purpose user I/O bank 2 |
| ピン 53 | I/O — General-purpose user I/O bank 2 |
| ピン 54 | I/O — General-purpose user I/O bank 2 |
| ピン 55 | I/O — General-purpose user I/O bank 2 |
| ピン 56 | I/O — General-purpose user I/O bank 2 |
| ピン 57 | I/O — General-purpose user I/O bank 2 |
| ピン 58 | I/O — General-purpose user I/O bank 2 |
| ピン 59 | I/O — General-purpose user I/O bank 2 |
| ピン 60 | I/O — General-purpose user I/O bank 2 |
| ピン 61 | I/O — General-purpose user I/O bank 2 |
| ピン 62 | GND — Ground |
| ピン 63 | I/O — General-purpose user I/O bank 3 |
| ピン 64 | I/O — General-purpose user I/O bank 3 |
| ピン 65 | I/O — General-purpose user I/O bank 3 |
| ピン 66 | I/O — General-purpose user I/O bank 3 |
| ピン 67 | I/O — General-purpose user I/O bank 3 |
| ピン 68 | I/O — General-purpose user I/O bank 3 |
| ピン 69 | I/O — General-purpose user I/O bank 3 |
| ピン 70 | I/O — General-purpose user I/O bank 3 |
| ピン 71 | I/O — General-purpose user I/O bank 3 |
| ピン 72 | I/O — General-purpose user I/O bank 3 |
| ピン 73 | I/O — General-purpose user I/O bank 3 |
| ピン 74 | I/O — General-purpose user I/O bank 3 |
| ピン 75 | VCCIO3 — I/O bank 3 supply voltage |
| ピン 76 | I/O — General-purpose user I/O bank 3 |
| ピン 77 | I/O — General-purpose user I/O bank 3 |
| ピン 78 | I/O — General-purpose user I/O bank 3 |
| ピン 79 | I/O — General-purpose user I/O bank 3 |
| ピン 80 | I/O — General-purpose user I/O bank 3 |
| ピン 81 | I/O — General-purpose user I/O bank 3 |
| ピン 82 | I/O — General-purpose user I/O bank 3 |
| ピン 83 | I/O — General-purpose user I/O bank 3 |
| ピン 84 | I/O — General-purpose user I/O bank 3 |
| ピン 85 | I/O — General-purpose user I/O bank 3 |
| ピン 86 | I/O — General-purpose user I/O bank 3 |
| ピン 87 | GND — Ground |
| ピン 88 | I/O — General-purpose user I/O bank 4 |
| ピン 89 | I/O — General-purpose user I/O bank 4 |
| ピン 90 | I/O — General-purpose user I/O bank 4 |
| ピン 91 | I/O — General-purpose user I/O bank 4 |
| ピン 92 | I/O — General-purpose user I/O bank 4 |
| ピン 93 | I/O — General-purpose user I/O bank 4 |
| ピン 94 | I/O — General-purpose user I/O bank 4 |
| ピン 95 | I/O — General-purpose user I/O bank 4 |
| ピン 96 | I/O — General-purpose user I/O bank 4 |
| ピン 97 | I/O — General-purpose user I/O bank 4 |
| ピン 98 | I/O — General-purpose user I/O bank 4 |
| ピン 99 | I/O — General-purpose user I/O bank 4 |
| ピン 100 | VCCIO4 — I/O bank 4 supply voltage |
| ピン 101 | I/O — General-purpose user I/O bank 4 |
| ピン 102 | I/O — General-purpose user I/O bank 4 |
| ピン 103 | I/O — General-purpose user I/O bank 4 |
| ピン 104 | I/O — General-purpose user I/O bank 4 |
| ピン 105 | I/O — General-purpose user I/O bank 4 |
| ピン 106 | I/O — General-purpose user I/O bank 4 |
| ピン 107 | I/O — General-purpose user I/O bank 4 |
| ピン 108 | I/O — General-purpose user I/O bank 4 |
| ピン 109 | I/O — General-purpose user I/O bank 4 |
| ピン 110 | I/O — General-purpose user I/O bank 4 |
| ピン 111 | I/O — General-purpose user I/O bank 4 |
| ピン 112 | GND — Ground |
| ピン 113 | TDI — JTAG Test Data In |
| ピン 114 | TMS — JTAG Test Mode Select |
| ピン 115 | TCK — JTAG Test Clock |
| ピン 116 | TDO — JTAG Test Data Out |
| ピン 117 | VCCINT — Core supply voltage (3.3V) |
| ピン 118 | nSTATUS — Configuration status (open-drain) |
| ピン 119 | CONF_DONE — Configuration done (open-drain) |
| ピン 120 | nCONFIG — Configuration start (active-low) |
| ピン 121 | MSEL0 — Configuration mode select 0 |
| ピン 122 | MSEL1 — Configuration mode select 1 |
| ピン 123 | MSEL2 — Configuration mode select 2 |
| ピン 124 | GND — Ground |
| ピン 125 | I/O — General-purpose user I/O bank 5 |
| ピン 126 | I/O — General-purpose user I/O bank 5 |
| ピン 127 | I/O — General-purpose user I/O bank 5 |
| ピン 128 | I/O — General-purpose user I/O bank 5 |
| ピン 129 | I/O — General-purpose user I/O bank 5 |
| ピン 130 | I/O — General-purpose user I/O bank 5 |
| ピン 131 | I/O — General-purpose user I/O bank 5 |
| ピン 132 | VCCIO5 — I/O bank 5 supply voltage |
| ピン 133 | I/O — General-purpose user I/O bank 5 |
| ピン 134 | I/O — General-purpose user I/O bank 5 |
| ピン 135 | I/O — General-purpose user I/O bank 5 |
| ピン 136 | I/O — General-purpose user I/O bank 5 |
| ピン 137 | I/O — General-purpose user I/O bank 5 |
| ピン 138 | I/O — General-purpose user I/O bank 5 |
| ピン 139 | I/O — General-purpose user I/O bank 5 |
| ピン 140 | I/O — General-purpose user I/O bank 5 |
| ピン 141 | I/O — General-purpose user I/O bank 5 |
| ピン 142 | GND — Ground |
| ピン 143 | I/O — General-purpose user I/O bank 5 |
| ピン 144 | I/O — General-purpose user I/O bank 5 |
主な用途
EPM570T144C3N の用途: 6 件s: Industrial Control Glue Logic, Communications Infrastructure I/O Bridging, Automotive Body Electronics, Microcontroller Expansion and Voltage Translation, Consumer Electronics Glue Logic, Prototyping and Rapid Design Iteration.
Industrial Control Glue Logic
The EPM570T144C3N is widely used as glue logic on industrial control boards where 116 user I/Os and 570 LEs provide ample capacity for I/O expansion and bus decode. Its 5.4 ns pin-to-pin propagation delay and ~300 MHz maximum frequency suit interrupt steering and high-speed register decoding between microcontrollers and peripherals. The 3.3V core and MultiVolt I/O support bridging to 1.5V, 1.8V, 2.5V, and 3.3V rails without external level shifters. The flash-based non-volatile configuration means the device is functional microseconds after power-up - ideal for factory-automation controllers that must respond deterministically the moment VCC stabilizes. JTAG-ISP enables field firmware updates.
おすすめ
Communications Infrastructure I/O Bridging
In routers, switches, and base-station line cards, the EPM570T144C3N bridges between ASIC/FPGA banks and backplane connectors operating at multiple voltage standards. The 116 user I/Os spread across the TQFP-144 footprint accommodate the high pin count needed for parallel bus expansion, while the LVCMOS/LVTTL/PCI/SSTL I/O standards supported by MultiVolt cover legacy 5V-tolerant interfaces. The 8 Kbit User Flash Memory block can store board revision IDs or boot-time configuration constants. With 5.4 ns tPD, the device introduces minimal latency in address decode and chip-select paths feeding the main processor.
おすすめ
Automotive Body Electronics
Although the EPM570T144C3N is commercial-temperature (0C to +85C), its MAX II architecture is also widely deployed on automotive body and infotainment boards for non-safety functions such as LED driving control, button matrix scanning, and CAN/LIN signal conditioning. The 5.4 ns propagation delay supports real-time LED PWM and button de-bounce logic. The 8 Kbit UFM can store calibration tables or board-identifying data. For under-hood or safety-critical automotive functions, engineers should migrate to the AEC-Q100 qualified MAX V family - but for body and infotainment the EPM570T144C3N remains a cost-effective, proven solution in volume production.
おすすめ
Microcontroller Expansion and Voltage Translation
The EPM570T144C3N is a classic choice for expanding a microcontroller's limited I/O count into 116 general-purpose pins while translating voltage levels between incompatible rails. MultiVolt I/O allow direct interfacing between a 1.8V MCU and 3.3V peripherals without external level shifters. With 570 LEs and 8 Kbit UFM, designers can implement protocol bridges, state machines, and timing-sensitive interfaces that would otherwise consume excessive MCU cycles. JTAG-ISP allows field firmware updates after the MCU has booted, supporting late-stage customization and factory provisioning.
おすすめ
Consumer Electronics Glue Logic
Replacing dozens of discrete 74-series logic chips, the EPM570T144C3N consolidates glue logic on consumer motherboards, set-top boxes, and display controllers. Its instant-on non-volatile configuration eliminates the boot-time latency that discrete PLDs and small FPGAs impose, enabling immediate response to user input. The 5.4 ns tPD supports high-speed interfaces such as LVDS signaling and parallel RGB routing, while the 116 user I/Os accommodate multiple connector pinouts. Quartus design entry and JTAG programming shorten development cycles and enable rapid board spin revisions.
おすすめ
Prototyping and Rapid Design Iteration
Designers prototyping new board designs favor the EPM570T144C3N because its Quartus design flow, JTAG in-system programmability, and instant-on behavior allow rapid hardware/software co-design iteration. Design changes can be downloaded in seconds via the JTAG header without removing the device or reprogramming a boot PROM. The 570 LEs and 8 Kbit UFM provide generous headroom for late-stage feature additions, and the TQFP-144 package is hand-solderable for low-volume prototyping. Once the design stabilizes, the same Quartus bitstream can be programmed into higher-density MAX II variants (EPM1270, EPM2210) without code changes.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: EPM570T144C3N — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | EPM570GT144C3N | EPM570T144C3 | EPM570T144-5 | EPM570T144A5N | EPM570T144C5N |
|---|---|---|---|---|---|---|
| Brand | Altera (now Intel) | Altera (now Intel) | Altera (now Intel) | Altera (now Intel) | Altera (now Intel) | Altera (now Intel) |
| Package | TQFP-144 | TQFP-144 - same | TQFP-144 - same | TQFP-144 - same | TQFP-144 - same | TQFP-144 - same |
| Logic Elements | 570 | 570 | 570 | 570 | 570 | 570 |
| Macrocells (typical) | 440 | 440 | 440 | 440 | 440 | 440 |
| User I/Os | 116 | 116 | 116 | 116 | 116 | 116 |
| tPD (max) | 5.4 ns | 5.4 ns | 5.4 ns | ~7.0 ns | ~8.0 ns | ~7.0 ns |
| Speed Grade | C3 | C3 | C3 | -5 | A5 | C5 |
| Core Voltage | 3.3 V | 3.3 V | 3.3 V | 3.3 V | 3.3 V | 3.3 V |
主な差別化要因
- C3 speed grade is the fastest commercial option （vs EPM570T144C5N)
- TQFP-144 footprint exposes 116 user I/Os （vs EPM570T100C5N)
- Non-volatile instant-on configuration （vs Small SRAM-based FPGAs)
設計ノート
Estimated: the EPM570T144C3N core draws approximately 30-50 mA quiescent plus dynamic current proportional to switching frequency. Place a 100 nF decoupling capacitor within 5 mm of every VCCINT and VCCIOx pin, plus a single 10 uF bulk tantalum or ceramic on each supply rail. TQFP-144 packages have multiple GND pins - connect all of them to a low-impedance ground plane for clean switching returns and reduced EMI. Avoid splitting the ground plane under the device to preserve signal integrity.
Route JTAG signals (TDI, TMS, TCK, TDO) as a daisy chain if multiple devices share the bus, with a 4.7 kohm pull-up on TCK and TMS per IEEE 1149.1 recommendations. Keep JTAG traces short and isolated from high-speed switching I/O to avoid programming failures. For 116 simultaneous switching outputs, use controlled-impedance traces and matched series termination to minimize reflections; refer to AN 224 (Altera) for high-speed PCB design guidelines.
Do not leave MSEL pins floating - strap them to defined logic levels per the MAX II handbook configuration mode table for the desired programming mode. The nCONFIG, nSTATUS, and CONF_DONE pins are open-drain and require external pull-ups; omitting these pull-ups prevents the device from entering user mode at power-up. The 8 Kbit UFM block has a finite endurance (~1000 cycles) and ~20-year data retention - verify these limits against your programming volume and field-life requirements.
コンプライアンス情報
RoHS compliant per Altera/Intel product page. Commercial temperature grade only - not AEC-Q100 qualified; for automotive safety-critical applications use MAX V family.