EPM570T144C3 - MAX II CPLD 440 LE 5.4ns TQFP-144 | Intel
部品番号: EPM570T144C3 ✓ 生産中| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $51.99 | $51.99 |
| 10 | $47.5 | $475.00 |
| 100 | $38.25 | $3,825.00 |
| 500 | $31.9 | $15,950.00 |
| 1,000 | $27.4 | $27,400.00 |
EPM570T144C3 概要
A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that combines the architecture of PAL/GAL with macro-cell arrays. It belongs to the broader category of programmable logic devices (PLDs), which sit alongside FPGAs as alternatives to fixed-function ASICs for glue logic, interface bridging, and state-machine implementation. CPLDs are characterized by instant-on behavior, deterministic timing, and high fan-in macrocells, making them ideal for control-plane applications.
Key features of the EPM570T144C3 include 440 Logic Elements distributed across 8 Logic Array Blocks, 160 user I/O pins, and 4.0 Kbits of user flash memory. The device supports in-system programmability (ISP) via IEEE 1149.1 JTAG, MultiVolt I/O for interfacing between 1.5 V, 1.8 V, 2.5 V, and 3.3 V logic domains, and operates over a commercial temperature range of 0 °C to +85 °C. The C3 speed grade provides a 5.4 ns tPD1 timing budget for high-speed control applications.
Architecturally, the EPM570T144C3 uses a non-volatile flash-based lookup table structure within each Logic Element, providing single-chip functionality without a separate boot PROM. The MultiVolt core and I/O allow mixed-voltage system integration, while the JTAG interface supports boundary-scan test and on-board reconfiguration in production environments.
Typical applications include bus interface bridging, power-up sequencing for multi-rail systems, I/O expansion and decoding logic, LED display drivers, and glue-logic replacement for discrete 74-series TTL. The wide I/O count and instant-on nature also suit industrial control and motor-drive front-end logic.
When designing with this part, ensure that the Quartus II or Intel Quartus Prime toolchain is used for synthesis and fitting; design files compiled for the MAX II device family are required. Decoupling capacitors should be placed close to all VCCINT and VCCIO pins.
This page synthesizes distributor pricing, same-family drop-in alternatives, and practical design notes for the EPM570T144C3 that are not duplicated on any single manufacturer datasheet or distributor listing.
ドロップイン代替品: EPM570T144C3 — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: EPM570T144C3 （同一形状・フットプリント） — 相違点: Programming Interface, Operating Temperature, Package, Process Technology, Maximum User I/O Pins.
クイック比較ツール — 並列比較する代替部品を選択:
EPM570T144C3N
✅ ドロップイン✓ 在庫あり
$9.6 / 個
データシートを見る →EPM570T144C4N
✅ ドロップイン✓ 在庫あり
$25.1 / 個
データシートを見る →EPM570T144C5N
✅ ドロップイン✓ 在庫あり
$9.35 / 個
データシートを見る →EPM570GT144C3
✅ ドロップイン ⚠️ 仕様未検証✓ 在庫あり
$13.5 / 個
データシートを見る →EPM570F256C3
✅ ドロップイン ⚠️ 仕様未検証✓ 在庫あり
$14.85 / 個
データシートを見る →EPM570T144C3 最大定格＆電気的特性
| Family | MAX II |
| Device | EPM570 |
| Logic Elements (LEs) | 440 |
| Macro Cells | 440 |
| Maximum User I/O Pins | 160 |
| User Flash Memory | 4.0 Kbits |
| Logic Array Blocks (LABs) | 8 |
| Speed Grade | C3 (5.4 ns tPD1) |
| Process Technology | 0.18 µm |
| Core Voltage (VCCINT) | 3.3 V (internal regulator generates 2.5 V core) |
| I/O Voltage (VCCIO) | 1.5 V / 1.8 V / 2.5 V / 3.3 V (MultiVolt I/O) |
| Maximum Frequency (internal) | 304 MHz |
| Propagation Delay (tPD1) | 5.4 ns |
| パッケージ | 144-pin TQFP (20 mm × 20 mm × 1.4 mm) |
| Operating Temperature (Commercial) | 0 °C to +85 °C |
| Programming Interface | IEEE 1149.1 JTAG (ISP) |
| Configuration | Non-volatile, instant-on (single-chip) |
EPM570T144C3 ピン構成
| ピン 1 | I/O — User I/O pin (bank 1) |
| ピン 2 | I/O — User I/O pin (bank 1) |
| ピン 3 | I/O — User I/O pin (bank 1) |
| ピン 4 | I/O — User I/O pin (bank 1) |
| ピン 5 | I/O — User I/O pin (bank 1) |
| ピン 6 | I/O — User I/O pin (bank 1) |
| ピン 7 | I/O — User I/O pin (bank 1) |
| ピン 8 | I/O — User I/O pin (bank 1) |
| ピン 9 | I/O — User I/O pin (bank 1) |
| ピン 10 | I/O — User I/O pin (bank 1) |
| ピン 11 | I/O — User I/O pin (bank 1) |
| ピン 12 | I/O — User I/O pin (bank 1) |
| ピン 13 | VCCIO1 — I/O bank 1 supply voltage |
| ピン 14 | I/O — User I/O pin (bank 1) |
| ピン 15 | I/O — User I/O pin (bank 1) |
| ピン 16 | I/O — User I/O pin (bank 1) |
| ピン 17 | I/O — User I/O pin (bank 1) |
| ピン 18 | I/O — User I/O pin (bank 1) |
| ピン 19 | I/O — User I/O pin (bank 1) |
| ピン 20 | I/O — User I/O pin (bank 1) |
| ピン 21 | GND — Ground |
| ピン 22 | I/O — User I/O pin (bank 2) |
| ピン 23 | I/O — User I/O pin (bank 2) |
| ピン 24 | I/O — User I/O pin (bank 2) |
| ピン 25 | I/O — User I/O pin (bank 2) |
| ピン 26 | I/O — User I/O pin (bank 2) |
| ピン 27 | I/O — User I/O pin (bank 2) |
| ピン 28 | I/O — User I/O pin (bank 2) |
| ピン 29 | I/O — User I/O pin (bank 2) |
| ピン 30 | I/O — User I/O pin (bank 2) |
| ピン 31 | I/O — User I/O pin (bank 2) |
| ピン 32 | I/O — User I/O pin (bank 2) |
| ピン 33 | I/O — User I/O pin (bank 2) |
| ピン 34 | VCCIO2 — I/O bank 2 supply voltage |
| ピン 35 | I/O — User I/O pin (bank 2) |
| ピン 36 | I/O — User I/O pin (bank 2) |
| ピン 37 | I/O — User I/O pin (bank 2) |
| ピン 38 | I/O — User I/O pin (bank 2) |
| ピン 39 | I/O — User I/O pin (bank 2) |
| ピン 40 | I/O — User I/O pin (bank 2) |
| ピン 41 | GND — Ground |
| ピン 42 | I/O — User I/O pin (bank 3) |
| ピン 43 | I/O — User I/O pin (bank 3) |
| ピン 44 | I/O — User I/O pin (bank 3) |
| ピン 45 | I/O — User I/O pin (bank 3) |
| ピン 46 | I/O — User I/O pin (bank 3) |
| ピン 47 | I/O — User I/O pin (bank 3) |
| ピン 48 | I/O — User I/O pin (bank 3) |
| ピン 49 | I/O — User I/O pin (bank 3) |
| ピン 50 | I/O — User I/O pin (bank 3) |
| ピン 51 | I/O — User I/O pin (bank 3) |
| ピン 52 | I/O — User I/O pin (bank 3) |
| ピン 53 | I/O — User I/O pin (bank 3) |
| ピン 54 | VCCIO3 — I/O bank 3 supply voltage |
| ピン 55 | I/O — User I/O pin (bank 3) |
| ピン 56 | I/O — User I/O pin (bank 3) |
| ピン 57 | I/O — User I/O pin (bank 3) |
| ピン 58 | I/O — User I/O pin (bank 3) |
| ピン 59 | I/O — User I/O pin (bank 3) |
| ピン 60 | I/O — User I/O pin (bank 3) |
| ピン 61 | GND — Ground |
| ピン 62 | I/O — User I/O pin (bank 4) |
| ピン 63 | I/O — User I/O pin (bank 4) |
| ピン 64 | I/O — User I/O pin (bank 4) |
| ピン 65 | I/O — User I/O pin (bank 4) |
| ピン 66 | I/O — User I/O pin (bank 4) |
| ピン 67 | I/O — User I/O pin (bank 4) |
| ピン 68 | I/O — User I/O pin (bank 4) |
| ピン 69 | I/O — User I/O pin (bank 4) |
| ピン 70 | I/O — User I/O pin (bank 4) |
| ピン 71 | I/O — User I/O pin (bank 4) |
| ピン 72 | I/O — User I/O pin (bank 4) |
| ピン 73 | I/O — User I/O pin (bank 4) |
| ピン 74 | VCCIO4 — I/O bank 4 supply voltage |
| ピン 75 | I/O — User I/O pin (bank 4) |
| ピン 76 | I/O — User I/O pin (bank 4) |
| ピン 77 | I/O — User I/O pin (bank 4) |
| ピン 78 | I/O — User I/O pin (bank 4) |
| ピン 79 | I/O — User I/O pin (bank 4) |
| ピン 80 | I/O — User I/O pin (bank 4) |
| ピン 81 | GND — Ground |
| ピン 82 | I/O — User I/O pin (bank 1) |
| ピン 83 | I/O — User I/O pin (bank 1) |
| ピン 84 | I/O — User I/O pin (bank 1) |
| ピン 85 | I/O — User I/O pin (bank 1) |
| ピン 86 | I/O — User I/O pin (bank 1) |
| ピン 87 | I/O — User I/O pin (bank 1) |
| ピン 88 | I/O — User I/O pin (bank 1) |
| ピン 89 | I/O — User I/O pin (bank 1) |
| ピン 90 | I/O — User I/O pin (bank 1) |
| ピン 91 | I/O — User I/O pin (bank 1) |
| ピン 92 | I/O — User I/O pin (bank 1) |
| ピン 93 | VCCINT — Internal core voltage (3.3 V, internal regulator generates 2.5 V core) |
| ピン 94 | I/O — User I/O pin (bank 1) |
| ピン 95 | I/O — User I/O pin (bank 1) |
| ピン 96 | I/O — User I/O pin (bank 1) |
| ピン 97 | I/O — User I/O pin (bank 1) |
| ピン 98 | I/O — User I/O pin (bank 1) |
| ピン 99 | I/O — User I/O pin (bank 1) |
| ピン 100 | I/O — User I/O pin (bank 1) |
| ピン 101 | GND — Ground |
| ピン 102 | I/O — User I/O pin (bank 2) |
| ピン 103 | I/O — User I/O pin (bank 2) |
| ピン 104 | I/O — User I/O pin (bank 2) |
| ピン 105 | I/O — User I/O pin (bank 2) |
| ピン 106 | I/O — User I/O pin (bank 2) |
| ピン 107 | I/O — User I/O pin (bank 2) |
| ピン 108 | I/O — User I/O pin (bank 2) |
| ピン 109 | I/O — User I/O pin (bank 2) |
| ピン 110 | I/O — User I/O pin (bank 2) |
| ピン 111 | I/O — User I/O pin (bank 2) |
| ピン 112 | I/O — User I/O pin (bank 2) |
| ピン 113 | I/O — User I/O pin (bank 2) |
| ピン 114 | VCCIO2 — I/O bank 2 supply voltage |
| ピン 115 | I/O — User I/O pin (bank 2) |
| ピン 116 | I/O — User I/O pin (bank 2) |
| ピン 117 | I/O — User I/O pin (bank 2) |
| ピン 118 | I/O — User I/O pin (bank 2) |
| ピン 119 | I/O — User I/O pin (bank 2) |
| ピン 120 | I/O — User I/O pin (bank 2) |
| ピン 121 | GND — Ground |
| ピン 122 | TMS — JTAG Test Mode Select |
| ピン 123 | TDI — JTAG Test Data In |
| ピン 124 | TCK — JTAG Test Clock |
| ピン 125 | I/O — User I/O pin (bank 4) |
| ピン 126 | I/O — User I/O pin (bank 4) |
| ピン 127 | I/O — User I/O pin (bank 4) |
| ピン 128 | I/O — User I/O pin (bank 4) |
| ピン 129 | I/O — User I/O pin (bank 4) |
| ピン 130 | I/O — User I/O pin (bank 4) |
| ピン 131 | I/O — User I/O pin (bank 4) |
| ピン 132 | I/O — User I/O pin (bank 4) |
| ピン 133 | I/O — User I/O pin (bank 4) |
| ピン 134 | I/O — User I/O pin (bank 4) |
| ピン 135 | I/O — User I/O pin (bank 4) |
| ピン 136 | VCCIO4 — I/O bank 4 supply voltage |
| ピン 137 | I/O — User I/O pin (bank 4) |
| ピン 138 | I/O — User I/O pin (bank 4) |
| ピン 139 | I/O — User I/O pin (bank 4) |
| ピン 140 | I/O — User I/O pin (bank 4) |
| ピン 141 | TDO — JTAG Test Data Out |
| ピン 142 | I/O — User I/O pin (bank 4) |
| ピン 143 | I/O — User I/O pin (bank 4) |
| ピン 144 | I/O — User I/O pin (bank 4) |
主な用途
EPM570T144C3 の用途: 7 件s: Bus Interface Bridging, Power-Up Sequencing Controller, Address Decoding and Chip-Select Generation, Industrial Control and Motor-Drive Front-End Logic, LED Display Driver and Multiplexing, Legacy TTL/CMOS Glue Logic Replacement, I/O Expansion for Microcontrollers.
Bus Interface Bridging
The EPM570T144C3 is well suited to bus-bridging tasks where a microprocessor must connect to peripherals with mismatched bus widths or voltages. Its 5.4 ns tPD1 propagation delay comfortably handles asynchronous 8/16/32-bit handshakes up to ~50 MHz, and its MultiVolt I/O supports direct 1.5 V, 1.8 V, 2.5 V, and 3.3 V signaling without level shifters. With 160 user I/O available in the TQFP-144, designers can implement full 32-bit address/data muxing plus control signal glue in a single device.
おすすめ
Power-Up Sequencing Controller
Power-up sequencers require deterministic timing and instant-on behavior - exactly the strengths of the EPM570T144C3. Because the device is non-volatile, it begins executing its state machine within microseconds of VCCINT reaching regulation, well before most analog rails stabilize. Its 440 LE are more than sufficient to implement multi-rail PG (power-good) chains with programmable delays using internal logic and a JTAG-updatable delay parameter. Compared with discrete RC sequencing networks, the CPLD approach enables in-system re-tuning without board rework.
おすすめ
Address Decoding and Chip-Select Generation
The EPM570T144C3 is a classic choice for address decoding in microcontroller and microprocessor systems where multiple peripherals share a bus. Its 5.4 ns tPD1 propagation delay introduces minimal wait-state insertion, and its 160 user I/O accommodate the wide address ranges typical of 32-bit cores. Designers can implement any decoding logic - full binary, partial, or windowed - and update it via JTAG ISP without re-spinning the board, dramatically shortening prototype iterations.
おすすめ
Industrial Control and Motor-Drive Front-End Logic
Industrial control panels often require deterministic glue logic for sensor conditioning, fault aggregation, and drive enable signals. The EPM570T144C3 supports up to 160 I/O, enabling direct interface to 24 V opto-isolated inputs and 3.3 V logic outputs via MultiVolt banks. Its instant-on non-volatile configuration prevents inrush misbehavior on cold-boot, and its 5.4 ns tPD1 timing supports deterministic fault-interlock response. For extended temperature ranges, the I-grade EPM570T144I3 variant is preferred where available in the same footprint.
おすすめ
LED Display Driver and Multiplexing
The EPM570T144C3 can drive LED matrix displays by multiplexing rows and columns with precise timing. Its 304 MHz maximum internal frequency and 5.4 ns tPD1 allow high-refresh-rate PWM generation for color-mixing or large dot-matrix panels. With 160 user I/O, the device can directly sink 16+ row/column lines per panel without external drivers, and the JTAG ISP allows firmware-updates for new display patterns without re-soldering.
おすすめ
Legacy TTL/CMOS Glue Logic Replacement
Designers often replace dozens of discrete 74-series TTL or 4000-series CMOS packages with a single EPM570T144C3, simplifying the BOM and reducing PCB area. The 440 LE are sufficient to implement encoders, decoders, multiplexers, latches, and small state machines that previously occupied a board corner. Because the configuration is non-volatile and field-updatable via JTAG, design bugs found in production can be patched without reworking the PCB.
おすすめ
I/O Expansion for Microcontrollers
When a microcontroller runs out of GPIO, the EPM570T144C3 can add up to 160 individually configurable I/O lines through a simple SPI or parallel interface. Each pin supports MultiVolt signaling, allowing the CPLD to talk to 1.8 V sensors and 3.3 V MCUs from a single device. The 5.4 ns tPD1 timing keeps I/O skew well under one SPI clock period, and the JTAG interface enables runtime I/O test and reconfiguration for safety-critical applications.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: EPM570T144C3 — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | EPM570T144C3N | EPM570T144C4N | EPM570T144C5N | EPM570GT144C3 | EPM570F256C3 |
|---|---|---|---|---|---|---|
| Brand | Intel | Intel | Intel | Intel | Intel | Intel |
| Package | TQFP-144 | TQFP-144 | TQFP-144 | TQFP-144 | TQFP-144 | TQFP-144 compatible (FineLine BGA migration) |
| Speed Grade | C3 (5.4 ns tPD1) | C3 (5.4 ns) | C4 (~6.5 ns) | C5 (~8.0 ns) | C3 (5.4 ns) | C3 (5.4 ns) |
| Logic Elements | 440 | 440 | 440 | 440 | 440 | 440 |
| User I/O Pins (max) | 160 | 160 | 160 | 160 | 160 | 160 |
| Operating Temperature | 0 C to +85 C (Commercial) | 0 C to +85 C | 0 C to +85 C | 0 C to +85 C | 0 C to +85 C | 0 C to +85 C |
| Lead-Free / RoHS | Unknown | Yes (Pb-free) | Yes (Pb-free) | Yes (Pb-free) | Yes (Pb-free, legacy G-suffix) | Depends on sub-suffix (N) |
主な差別化要因
- Instant-on non-volatile configuration eliminates external boot PROM （vs EPM570F256C3 (FineLine BGA migration option))
- 160 user I/O pins in a 0.5 mm pitch TQFP - highest count in MAX II family for this package （vs EPM240T100C3 (TQFP-100))
- MultiVolt I/O supports 1.5 V, 1.8 V, 2.5 V, and 3.3 V in a single device （vs Discrete 74-series TTL glue logic)
設計ノート
The EPM570T144C3 requires a 3.3 V supply on VCCINT (an internal LDO generates the 2.5 V core), and each of the four I/O banks (VCCIO1-4) may be powered independently at 1.5 V, 1.8 V, 2.5 V, or 3.3 V. Place one 0.1 µF decoupling capacitor within 2 mm of every VCCINT and VCCIO pin, plus a single 10 µF bulk capacitor per bank to suppress switching transients during ISP programming. Avoid powering VCCIO at a voltage not supported by the chosen I/O standard.
The 144-pin TQFP package has a 0.5 mm pitch and 20 mm × 20 mm body, which demands careful trace escape routing. Use 0.15 mm/0.20 mm trace/space between TQFP fingers and fan out to inner power planes on the second layer. Keep all four I/O bank supplies (VCCIO1-4) on a single plane region if possible, and provide at least one continuous GND plane beneath the device for return-path integrity during JTAG boundary-scan.
Pin 1 is located at the top-left of the TQFP-144 package when the dot marker is oriented to the upper-left. The JTAG signals TCK (pin 124), TMS (pin 122), TDI (pin 123), and TDO (pin 141) must be routed away from high-frequency switching signals and length-matched within 25 mm to avoid boundary-scan failures. A 10 kΩ pull-up on TDI and TMS, plus a 10 kΩ pull-up on TDO, is recommended for stable JTAG operation.
Do not confuse the speed-grade suffix C3 (fastest, 5.4 ns) with C5 (slowest, ~8.0 ns) when substituting across production runs - timing closure may fail. The 'T' prefix in EPM570T144 indicates TQFP package, while 'G' and 'F' prefixes denote legacy lead-free and FineLine BGA migration options. Always re-validate the Quartus II fitter report after a speed-grade or package-marker change.
Although CPLD outputs have slower edge rates than FPGAs (typically 2-3 ns), the 5.4 ns tPD1 timing budget assumes a 50 pF load. For high-fanout signals driving more than eight inputs or external cables, add a series 22 Ω damping resistor close to the CPLD output to limit overshoot and ringing. For MultiVolt I/O banks, mix only compatible voltage standards in the same bank - mixing 1.5 V and 3.3 V in one bank is not allowed.
コンプライアンス情報
RoHS/lead-free status was not confirmed in the verified web data; the EPM570T144C3N variant is documented as Pb-free. AEC-Q100 is not applicable to a general-purpose commercial CPLD. Conflict-minerals statement available from Intel's Corporate Responsibility Report.
