EPM570T144C4N - 570 LE MAX II CPLD, 144-TQFP | Intel
MPN: EPM570T144C4N ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $36.15 | $36.15 |
| 10 | $33.2 | $332.00 |
| 100 | $29.85 | $2,985.00 |
| 500 | $27.4 | $13,700.00 |
| 1,000 | $25.1 | $25,100.00 |
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View Datasheet →EPM570T144C4N Maximum Ratings & Electrical Characteristics
| Family | MAX II |
| Logic Elements (LE) | 570 |
| Equivalent Macrocells | 440 |
| Maximum User I/O Pins | 212 (package-dependent; TQFP-144 user count varies) |
| User Flash Memory (UFM) | 8 Kbits |
| Process Technology | 0.18 µm flash CMOS, 6-layer metal |
| Maximum Internal Frequency (fMAX) | 247.5 MHz |
| Pin-to-Pin Propagation Delay (tPD) | 5.4 ns (C4 speed grade) |
| Core Supply Voltage (VCCINT) | 2.5 V / 3.3 V (MultiVolt core) |
| I/O Supply Voltage (VCCIO) | 1.5 V / 1.8 V / 2.5 V / 3.3 V (MultiVolt I/O) |
| Programming Interface | JTAG (IEEE 1149.1) with in-system programmability (ISP) |
| Operating Temperature | -40 °C to +85 °C (industrial, suffix N) |
| Package | TQFP-144 (22 × 22 mm, 0.5 mm pitch) |
| Mounting Type | Surface Mount |
| MSL Level | 3 (per JEDEC J-STD-020) |
| Lead-Free / RoHS | Lead-free, RoHS compliant |
| Global Clock Networks | 4 |
| Non-Volatile Configuration | Yes (instant-on, no external boot PROM required) |
EPM570T144C4N Pin Configuration
| Pin 1 | I/O — General-purpose user I/O (bank 1) |
| Pin 2 | I/O — General-purpose user I/O (bank 1) |
| Pin 3 | I/O — General-purpose user I/O (bank 1) |
| Pin 4 | I/O — General-purpose user I/O (bank 1) |
| Pin 5 | I/O — General-purpose user I/O (bank 1) |
| Pin 6 | I/O — General-purpose user I/O (bank 1) |
| Pin 7 | I/O — General-purpose user I/O (bank 1) |
| Pin 8 | I/O — General-purpose user I/O (bank 1) |
| Pin 9 | I/O — General-purpose user I/O (bank 1) |
| Pin 10 | I/O — General-purpose user I/O (bank 1) |
| Pin 11 | VCCIO1 — I/O supply voltage for bank 1 (1.5V/1.8V/2.5V/3.3V) |
| Pin 12 | I/O — General-purpose user I/O (bank 1) |
| Pin 13 | I/O — General-purpose user I/O (bank 1) |
| Pin 14 | I/O — General-purpose user I/O (bank 1) |
| Pin 15 | I/O — General-purpose user I/O (bank 1) |
| Pin 16 | I/O — General-purpose user I/O (bank 1) |
| Pin 17 | I/O — General-purpose user I/O (bank 1) |
| Pin 18 | I/O — General-purpose user I/O (bank 1) |
| Pin 19 | I/O — General-purpose user I/O (bank 1) |
| Pin 20 | I/O — General-purpose user I/O (bank 1) |
| Pin 21 | GND — Ground |
| Pin 22 | I/O — General-purpose user I/O (bank 2) |
| Pin 23 | I/O — General-purpose user I/O (bank 2) |
| Pin 24 | I/O — General-purpose user I/O (bank 2) |
| Pin 25 | I/O — General-purpose user I/O (bank 2) |
| Pin 26 | I/O — General-purpose user I/O (bank 2) |
| Pin 27 | I/O — General-purpose user I/O (bank 2) |
| Pin 28 | I/O — General-purpose user I/O (bank 2) |
| Pin 29 | I/O — General-purpose user I/O (bank 2) |
| Pin 30 | I/O — General-purpose user I/O (bank 2) |
| Pin 31 | I/O — General-purpose user I/O (bank 2) |
| Pin 32 | I/O — General-purpose user I/O (bank 2) |
| Pin 33 | VCCIO2 — I/O supply voltage for bank 2 (1.5V/1.8V/2.5V/3.3V) |
| Pin 34 | I/O — General-purpose user I/O (bank 2) |
| Pin 35 | I/O — General-purpose user I/O (bank 2) |
| Pin 36 | I/O — General-purpose user I/O (bank 2) |
| Pin 37 | I/O — General-purpose user I/O (bank 2) |
| Pin 38 | I/O — General-purpose user I/O (bank 2) |
| Pin 39 | I/O — General-purpose user I/O (bank 2) |
| Pin 40 | I/O — General-purpose user I/O (bank 2) |
| Pin 41 | I/O — General-purpose user I/O (bank 2) |
| Pin 42 | GND — Ground |
| Pin 43 | I/O — General-purpose user I/O (bank 3) |
| Pin 44 | I/O — General-purpose user I/O (bank 3) |
| Pin 45 | I/O — General-purpose user I/O (bank 3) |
| Pin 46 | I/O — General-purpose user I/O (bank 3) |
| Pin 47 | I/O — General-purpose user I/O (bank 3) |
| Pin 48 | I/O — General-purpose user I/O (bank 3) |
| Pin 49 | I/O — General-purpose user I/O (bank 3) |
| Pin 50 | I/O — General-purpose user I/O (bank 3) |
| Pin 51 | I/O — General-purpose user I/O (bank 3) |
| Pin 52 | I/O — General-purpose user I/O (bank 3) |
| Pin 53 | I/O — General-purpose user I/O (bank 3) |
| Pin 54 | I/O — General-purpose user I/O (bank 3) |
| Pin 55 | VCCIO3 — I/O supply voltage for bank 3 (1.5V/1.8V/2.5V/3.3V) |
| Pin 56 | I/O — General-purpose user I/O (bank 3) |
| Pin 57 | I/O — General-purpose user I/O (bank 3) |
| Pin 58 | I/O — General-purpose user I/O (bank 3) |
| Pin 59 | I/O — General-purpose user I/O (bank 3) |
| Pin 60 | I/O — General-purpose user I/O (bank 3) |
| Pin 61 | I/O — General-purpose user I/O (bank 3) |
| Pin 62 | I/O — General-purpose user I/O (bank 3) |
| Pin 63 | I/O — General-purpose user I/O (bank 3) |
| Pin 64 | GND — Ground |
| Pin 65 | I/O — General-purpose user I/O (bank 4) |
| Pin 66 | I/O — General-purpose user I/O (bank 4) |
| Pin 67 | I/O — General-purpose user I/O (bank 4) |
| Pin 68 | I/O — General-purpose user I/O (bank 4) |
| Pin 69 | I/O — General-purpose user I/O (bank 4) |
| Pin 70 | I/O — General-purpose user I/O (bank 4) |
| Pin 71 | I/O — General-purpose user I/O (bank 4) |
| Pin 72 | I/O — General-purpose user I/O (bank 4) |
| Pin 73 | I/O — General-purpose user I/O (bank 4) |
| Pin 74 | I/O — General-purpose user I/O (bank 4) |
| Pin 75 | I/O — General-purpose user I/O (bank 4) |
| Pin 76 | I/O — General-purpose user I/O (bank 4) |
| Pin 77 | VCCIO4 — I/O supply voltage for bank 4 (1.5V/1.8V/2.5V/3.3V) |
| Pin 78 | I/O — General-purpose user I/O (bank 4) |
| Pin 79 | I/O — General-purpose user I/O (bank 4) |
| Pin 80 | I/O — General-purpose user I/O (bank 4) |
| Pin 81 | I/O — General-purpose user I/O (bank 4) |
| Pin 82 | I/O — General-purpose user I/O (bank 4) |
| Pin 83 | I/O — General-purpose user I/O (bank 4) |
| Pin 84 | I/O — General-purpose user I/O (bank 4) |
| Pin 85 | I/O — General-purpose user I/O (bank 4) |
| Pin 86 | GND — Ground |
| Pin 87 | TDI — JTAG Test Data In (with internal weak pull-up) |
| Pin 88 | TMS — JTAG Test Mode Select (with internal weak pull-up) |
| Pin 89 | TCK — JTAG Test Clock (with internal weak pull-down) |
| Pin 90 | TDO — JTAG Test Data Out |
| Pin 91 | I/O — General-purpose user I/O (bank 4) |
| Pin 92 | I/O — General-purpose user I/O (bank 4) |
| Pin 93 | I/O — General-purpose user I/O (bank 4) |
| Pin 94 | I/O — General-purpose user I/O (bank 4) |
| Pin 95 | I/O — General-purpose user I/O (bank 4) |
| Pin 96 | I/O — General-purpose user I/O (bank 4) |
| Pin 97 | I/O — General-purpose user I/O (bank 4) |
| Pin 98 | I/O — General-purpose user I/O (bank 4) |
| Pin 99 | I/O — General-purpose user I/O (bank 4) |
| Pin 100 | I/O — General-purpose user I/O (bank 4) |
| Pin 101 | VCCINT — Core supply voltage (2.5V or 3.3V) |
| Pin 102 | GND — Ground |
| Pin 103 | I/O — General-purpose user I/O (bank 3) |
| Pin 104 | I/O — General-purpose user I/O (bank 3) |
| Pin 105 | I/O — General-purpose user I/O (bank 3) |
| Pin 106 | I/O — General-purpose user I/O (bank 3) |
| Pin 107 | I/O — General-purpose user I/O (bank 3) |
| Pin 108 | I/O — General-purpose user I/O (bank 3) |
| Pin 109 | I/O — General-purpose user I/O (bank 3) |
| Pin 110 | I/O — General-purpose user I/O (bank 3) |
| Pin 111 | I/O — General-purpose user I/O (bank 3) |
| Pin 112 | I/O — General-purpose user I/O (bank 3) |
| Pin 113 | I/O — General-purpose user I/O (bank 3) |
| Pin 114 | I/O — General-purpose user I/O (bank 3) |
| Pin 115 | I/O — General-purpose user I/O (bank 3) |
| Pin 116 | I/O — General-purpose user I/O (bank 3) |
| Pin 117 | I/O — General-purpose user I/O (bank 3) |
| Pin 118 | I/O — General-purpose user I/O (bank 3) |
| Pin 119 | I/O — General-purpose user I/O (bank 3) |
| Pin 120 | I/O — General-purpose user I/O (bank 3) |
| Pin 121 | I/O — General-purpose user I/O (bank 2) |
| Pin 122 | I/O — General-purpose user I/O (bank 2) |
| Pin 123 | I/O — General-purpose user I/O (bank 2) |
| Pin 124 | I/O — General-purpose user I/O (bank 2) |
| Pin 125 | I/O — General-purpose user I/O (bank 2) |
| Pin 126 | I/O — General-purpose user I/O (bank 2) |
| Pin 127 | I/O — General-purpose user I/O (bank 2) |
| Pin 128 | I/O — General-purpose user I/O (bank 2) |
| Pin 129 | I/O — General-purpose user I/O (bank 2) |
| Pin 130 | I/O — General-purpose user I/O (bank 2) |
| Pin 131 | I/O — General-purpose user I/O (bank 2) |
| Pin 132 | I/O — General-purpose user I/O (bank 2) |
| Pin 133 | I/O — General-purpose user I/O (bank 2) |
| Pin 134 | I/O — General-purpose user I/O (bank 2) |
| Pin 135 | I/O — General-purpose user I/O (bank 1) |
| Pin 136 | I/O — General-purpose user I/O (bank 1) |
| Pin 137 | I/O — General-purpose user I/O (bank 1) |
| Pin 138 | I/O — General-purpose user I/O (bank 1) |
| Pin 139 | I/O — General-purpose user I/O (bank 1) |
| Pin 140 | I/O — General-purpose user I/O (bank 1) |
| Pin 141 | I/O — General-purpose user I/O (bank 1) |
| Pin 142 | I/O — General-purpose user I/O (bank 1) |
| Pin 143 | I/O — General-purpose user I/O (bank 1) |
| Pin 144 | GND — Ground |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM570T144C4N is suitable for 6 applications: Microcontroller I/O Expansion & Glue Logic, Bus Protocol Bridging (I2C/SPI/UART/CAN), Power Supply Sequencing & Supervisory Logic, LED Display Drivers & Scan Matrix Control, JTAG-Based Board Test Infrastructure (ICT/BIST), Industrial PLC & Motor Control Logic.
Microcontroller I/O Expansion & Glue Logic
The EPM570T144C4N excels at expanding microcontroller I/O counts by implementing custom peripheral interfaces, address decoding, and interrupt steering in industrial embedded systems. Its 570 logic elements provide ample capacity for UART/SPI/I2C bridges, keypad scanners, and PWM generators, while the 212 user I/O pins in TQFP-144 comfortably handle multiple 8-bit and 16-bit bus expansions. The 5.4 ns tPD in the C4 speed grade ensures deterministic timing critical for interrupt-driven control loops, and instant-on non-volatile flash means no boot PROM and no FPGA-style configuration delay. Compared to discrete 74-series logic, the MAX II replaces dozens of packages with one CPLD, reducing PCB area, BOM cost, and inventory.
Recommended
Bus Protocol Bridging (I2C/SPI/UART/CAN)
The EPM570T144C4N is widely deployed as a bus-bridge translator between microcontrollers, sensors, and ASICs operating at mismatched voltages and protocols. Its MultiVolt I/O supports 1.5V, 1.8V, 2.5V, 3.3V, and 5.0V signaling on a per-bank basis, eliminating external level shifters. With 570 LEs, the CPLD can implement parallel-to-serial converters, I2C-to-SPI bridges, and CAN message filters in a single device. The 4.5–5.4 ns tPD keeps latency low for real-time bus arbitration. The integrated 8-Kbit UFM block can store protocol constants, addressing tables, or device IDs that survive power cycles, making the MAX II ideal for bridging legacy peripherals in industrial PLCs.
Recommended
Power Supply Sequencing & Supervisory Logic
The EPM570T144C4N's instant-on flash-based architecture (typical <1 ms to active I/O) makes it ideal for power-supply sequencing in multi-rail systems such as FPGAs, SoCs, and RF transceivers that require strict rail-on ordering. Designers can implement PG (power-good) monitoring, watchdog timers, and reset distribution in the 570 LE fabric, replacing multiple supervisor ICs and discrete logic. The MultiVolt I/O interfaces directly with 1.0V to 3.3V rails without level shifters. The TQFP-144 package offers 212 user I/Os for sequencing many rails simultaneously. Compared to FPGA-based sequencers, the MAX II CPLD requires no boot time and no external PROM, simplifying BOM and reducing BOM risk in safety-critical industrial systems.
Recommended
LED Display Drivers & Scan Matrix Control
The EPM570T144C4N drives large LED dot-matrix displays, seven-segment panels, and signage arrays by handling row/column scanning, PWM dimming, and refresh-rate generation in a single device. Its 247.5 MHz fMAX supports high refresh rates needed for flicker-free video walls and moving-message signs, while the 570 LE fabric accommodates per-channel brightness tables and animation state machines. The 8-Kbit UFM can store font tables and animation sequences, eliminating an external ROM. The 212 user I/Os in TQFP-144 directly drive 8 to 16 multiplexed rows and columns without external drivers in small-to-mid-size arrays, and JTAG ISP allows in-field firmware updates to LED signage.
Recommended
JTAG-Based Board Test Infrastructure (ICT/BIST)
The EPM570T144C4N integrates seamlessly into JTAG-based in-circuit test (ICT) and boundary-scan test (BST) infrastructure via its IEEE 1149.1 compliant TAP controller. Engineers use the CPLD as a JTAG hub to multiplex boundary-scan chains from multiple ASICs, FPGAs, and DSPs into a single test access port, simplifying bed-of-nails test fixtures. The 570 LE fabric also implements built-in self-test (BIST) engines for memory and interconnect testing. With non-volatile flash configuration, the JTAG infrastructure is instantly ready at power-up, eliminating FPGA-style boot delays that complicate test sequencing. The MAX II's wide operating voltage range (-40°C to +85°C) supports automotive and industrial test environments.
Recommended
Industrial PLC & Motor Control Logic
The EPM570T144C4N delivers deterministic, real-time logic for industrial PLCs, servo drives, and stepper motor controllers where instant-on response and noise immunity are critical. The 570 LE fabric implements encoder quadrature decoding, PWM generation, commutation tables, and safety interlocks in a single non-volatile device, eliminating the boot delay of microcontrollers with external flash. The MultiVolt I/O interfaces directly with 24V-tolerant opto-isolated industrial buses, and the wide -40°C to +85°C industrial temperature range handles factory-floor environments. The 247.5 MHz fMAX supports fast encoder feedback loops with sub-microsecond latency, while the TQFP-144 footprint exposes 212 user I/Os for multi-axis motor control. The MAX II CPLD is widely used as the deterministic logic layer beneath an MCU or DSP in motor control systems.
Recommended
Recommended Products Summary
Engineering reference data for EPM570T144C4N — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM570T144C4 | EPM570GT144C4N | EPM570T144C5N | EPM570T144A5N | EPM570T144C3N |
|---|---|---|---|---|---|---|
| Package | TQFP-144 (22x22 mm, 0.5 mm pitch) | TQFP-144 (22x22 mm, 0.5 mm pitch) - same | TQFP-144 (22x22 mm, 0.5 mm pitch) - same | TQFP-144 (22x22 mm, 0.5 mm pitch) - same | TQFP-144 (22x22 mm, 0.5 mm pitch) - same | TQFP-144 (22x22 mm, 0.5 mm pitch) - same |
| Brand | Intel (formerly Altera) | Intel | Intel | Intel | Intel | Intel |
| Logic Elements | 570 | 570 | 570 | 570 | 570 | 570 |
| Equivalent Macrocells | 440 | 440 | 440 | 440 | 440 | 440 |
| Speed Grade (tPD) | C4 (~5.4 ns pin-to-pin) | C4 (~5.4 ns) | C4 (~5.4 ns) | C5 (~4.5 ns, faster) | A5 (automotive temp) | C3 (~7 ns, slower) |
| Family Variant | MAX II (standard) | MAX II | MAX II G (green, lower static power) | MAX II | MAX II (automotive) | MAX II |
| Operating Temperature | -40C to +85C (industrial) | 0C to +85C (commercial, non-N) | -40C to +85C (industrial) | -40C to +85C (industrial) | -40C to +125C (automotive, extended) | -40C to +85C (industrial) |
| User Flash Memory (UFM) | 8 Kbits | 8 Kbits | 8 Kbits | 8 Kbits | 8 Kbits | 8 Kbits |
| Programming Interface | JTAG (IEEE 1149.1) ISP | JTAG (IEEE 1149.1) ISP | JTAG (IEEE 1149.1) ISP | JTAG (IEEE 1149.1) ISP | JTAG (IEEE 1149.1) ISP | JTAG (IEEE 1149.1) ISP |
Key Differentiators
- 570 logic elements vs EPM240's 240 LEs - 2.4x capacity (vs EPM240T100C5N)
- Industrial -40C to +85C temperature range (vs EPM570T144C4 (commercial, non-N))
- TQFP-144 with 212 user I/Os vs TQFP-100's 76 user I/Os (vs EPM570T100C4N)
Design Notes
Decouple every VCCINT and VCCIO pin with a 0.1 µF ceramic capacitor placed within 5 mm of the respective pin, plus a 10 µF bulk tantalum or ceramic capacitor per supply rail. The MAX II datasheet recommends one bulk capacitor per VCCIO bank. Tie all VCCINT pins to a single 2.5 V or 3.3 V rail; do not mix core voltages. Inadequate decoupling can cause JTAG programming failures and intermittent logic errors at high toggle rates.
Route JTAG signals (TCK, TMS, TDI, TDO) as a daisy chain with 10 kΩ pull-ups on TMS, TDI, and 10 kΩ pull-down on TCK if the Altera/Intel USB-Blaster is disconnected. Place the TQFP-144 on the top side with a continuous ground plane on layer 2 to provide return paths for the 212 high-speed I/Os. The 0.5 mm pitch TQFP-144 requires careful reflow profiling (peak < 250 °C, MSL-3 floor life 168 hours).
Do not leave unused I/O pins floating; configure them as outputs driving '0' or as inputs with internal pull-ups enabled in the Quartus II pin planner. Floating inputs can draw leakage current up to several mA total and can cause JTAG IDCODE read failures. Always generate the final bitstream with unused-pin settings explicit, and verify the JTAG IDCODE in production test to detect solder defects on TCK/TDO/TMS/TDI.
Compliance Information
RoHS compliant and lead-free per Altera/Intel material declaration. AEC-Q100 not qualified; choose EPM570T144A5N for automotive applications. Halogen-free status not explicitly stated in provided web data.
