EPM7128AETC144-10 - 128-Macrocell MAX 7000A CPLD, 10ns TQFP-144
部品番号: EPM7128AETC144-10 ✗ 生産終了| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $36.17 | $36.17 |
| 10 | $32.55 | $325.50 |
| 100 | $28.93 | $2,893.00 |
| 500 | $25.32 | $12,660.00 |
| 1,000 | $21.7 | $21,700.00 |
EPM7128AETC144-10 概要
A CPLD (Complex Programmable Logic Device) is a non-volatile, instant-on programmable logic device that sits between discrete glue-logic ICs and larger FPGAs. The MAX 7000A family uses an EEPROM-based architecture: macrocells, a programmable interconnect array (PIA), and I/O control blocks. The hierarchy is: macrocell -> logic array block (LAB) -> CPLD -> programmable logic -> semiconductor. CPLDs are typically chosen when designers need deterministic timing, low standby power, and instant-on behavior without an external configuration memory.
Key features of the EPM7128AETC144-10 include in-system programmability through IEEE Std. 1149.1 JTAG, an internal 3.3V regulator that accepts 2.5V/3.3V/5V I/O voltages, four dedicated inputs that double as global clock/clear/control signals, 36 user I/Os, and pin-compatible migration across the MAX 7000A density range. Each macrocell contains a programmable AND/OR array with a configurable register that can be set up as D, T, JK, or SR flip-flops.
Typical applications include bus interface bridging, address decoding, state-machine control, peripheral glue logic, and I/O expansion in industrial controllers, telecom line cards, and legacy 5V/3.3V mixed-voltage systems. Its 100% non-volatile EEPROM cells allow instant-on operation suitable for boot-loaders and deterministic interrupt-driven control.
When designing with this part, populate the JTAG chain with TCK/TMS/TDI/TDO, route OE1/OE2/GCLK1/GCLK2/GCLRn/CEO to global pins, and provide bulk decoupling of 100 uF plus 0.1 uF near each supply pin. Pin compatibility within the MAX 7000A family allows 64-, 128-, 192-, and 256-macrocell devices in the same 144-TQFP footprint. This page synthesizes distributor pricing, MAX 7000A drop-in alternatives, and practical design notes that go beyond the manufacturer datasheet.
ドロップイン代替品: EPM7128AETC144-10 — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: EPM7128AETC144-10 （同一形状・フットプリント） — 相違点: Package, Operating Temperature, Supply Voltage (VCCINT), Process Technology, Programming Interface.
クイック比較ツール — 並列比較する代替部品を選択:
EPM7128AETC144-10N
✅ ドロップイン✓ 在庫あり
$22.56 / 個
データシートを見る →EPM7128AETC144-7
✅ ドロップイン✓ 在庫あり
$16.4 / 個
データシートを見る →EPM7128AETC144-15
✅ ドロップイン ⚠️ 仕様未検証📋 参考代替品（カタログ未掲載）
EPM7128AETI144-7
✅ ドロップイン ⚠️ 仕様未検証📋 参考代替品（カタログ未掲載）
EPM7128AETC144-10 最大定格＆電気的特性
| Family | MAX 7000A |
| Macrocells | 128 |
| Usable Gates | 2,500 |
| Logic Array Blocks (LABs) | 8 |
| Maximum User I/Os | 36 |
| Pin-to-pin Logic Delay (tPD) | 10 ns |
| Maximum Internal Counter Frequency | 98 MHz |
| Supply Voltage (Core) | 3.3 V |
| I/O Voltage Tolerance | 2.5 V / 3.3 V / 5 V |
| 動作温度 | 0C to +70C (Commercial) |
| パッケージ | 144-pin TQFP (also referred to as LQFP-144) |
| Programming Interface | JTAG (IEEE Std. 1149.1) and ByteBlaster |
| Non-volatile Memory | EEPROM, instant-on |
| Global Clocks / Global OE | 2 / 2 |
| 実装タイプ | Surface Mount |
| MSLレベル | MSL 3 (per JEDEC J-STD-020) |
EPM7128AETC144-10 ピン構成
| ピン 1 | OE1 — Global output enable 1 (active low) |
| ピン 2 | GCLRn — Global clear (active low) |
| ピン 3 | I/O — User I/O pin (bank 1) |
| ピン 4 | I/O — User I/O pin (bank 1) |
| ピン 5 | I/O — User I/O pin (bank 1) |
| ピン 6 | I/O — User I/O pin (bank 1) |
| ピン 7 | I/O — User I/O pin (bank 1) |
| ピン 8 | I/O — User I/O pin (bank 1) |
| ピン 9 | GND — Ground |
| ピン 10 | I/O — User I/O pin (bank 1) |
| ピン 11 | I/O — User I/O pin (bank 1) |
| ピン 12 | I/O — User I/O pin (bank 1) |
| ピン 13 | I/O — User I/O pin (bank 1) |
| ピン 14 | I/O — User I/O pin (bank 1) |
| ピン 15 | I/O — User I/O pin (bank 1) |
| ピン 16 | GND — Ground |
| ピン 17 | I/O — User I/O pin (bank 2) |
| ピン 18 | I/O — User I/O pin (bank 2) |
| ピン 19 | I/O — User I/O pin (bank 2) |
| ピン 20 | I/O — User I/O pin (bank 2) |
| ピン 21 | I/O — User I/O pin (bank 2) |
| ピン 22 | I/O — User I/O pin (bank 2) |
| ピン 23 | GND — Ground |
| ピン 24 | I/O — User I/O pin (bank 2) |
| ピン 25 | I/O — User I/O pin (bank 2) |
| ピン 26 | I/O — User I/O pin (bank 2) |
| ピン 27 | I/O — User I/O pin (bank 2) |
| ピン 28 | I/O — User I/O pin (bank 2) |
| ピン 29 | I/O — User I/O pin (bank 2) |
| ピン 30 | GND — Ground |
| ピン 31 | I/O — User I/O pin (bank 2) |
| ピン 32 | I/O — User I/O pin (bank 2) |
| ピン 33 | I/O — User I/O pin (bank 2) |
| ピン 34 | I/O — User I/O pin (bank 2) |
| ピン 35 | I/O — User I/O pin (bank 2) |
| ピン 36 | I/O — User I/O pin (bank 2) |
| ピン 37 | GND — Ground |
| ピン 38 | I/O — User I/O pin (bank 3) |
| ピン 39 | I/O — User I/O pin (bank 3) |
| ピン 40 | I/O — User I/O pin (bank 3) |
| ピン 41 | I/O — User I/O pin (bank 3) |
| ピン 42 | I/O — User I/O pin (bank 3) |
| ピン 43 | GCLK1 — Global clock input 1 |
| ピン 44 | GCLK2 — Global clock input 2 |
| ピン 45 | I/O — User I/O pin (bank 3) |
| ピン 46 | I/O — User I/O pin (bank 3) |
| ピン 47 | I/O — User I/O pin (bank 3) |
| ピン 48 | I/O — User I/O pin (bank 3) |
| ピン 49 | I/O — User I/O pin (bank 3) |
| ピン 50 | I/O — User I/O pin (bank 3) |
| ピン 51 | I/O — User I/O pin (bank 3) |
| ピン 52 | GND — Ground |
| ピン 53 | I/O — User I/O pin (bank 3) |
| ピン 54 | I/O — User I/O pin (bank 3) |
| ピン 55 | I/O — User I/O pin (bank 3) |
| ピン 56 | I/O — User I/O pin (bank 3) |
| ピン 57 | I/O — User I/O pin (bank 3) |
| ピン 58 | I/O — User I/O pin (bank 3) |
| ピン 59 | GND — Ground |
| ピン 60 | I/O — User I/O pin (bank 4) |
| ピン 61 | I/O — User I/O pin (bank 4) |
| ピン 62 | I/O — User I/O pin (bank 4) |
| ピン 63 | I/O — User I/O pin (bank 4) |
| ピン 64 | I/O — User I/O pin (bank 4) |
| ピン 65 | I/O — User I/O pin (bank 4) |
| ピン 66 | I/O — User I/O pin (bank 4) |
| ピン 67 | I/O — User I/O pin (bank 4) |
| ピン 68 | I/O — User I/O pin (bank 4) |
| ピン 69 | GND — Ground |
| ピン 70 | I/O — User I/O pin (bank 4) |
| ピン 71 | I/O — User I/O pin (bank 4) |
| ピン 72 | I/O — User I/O pin (bank 4) |
| ピン 73 | I/O — User I/O pin (bank 4) |
| ピン 74 | I/O — User I/O pin (bank 4) |
| ピン 75 | I/O — User I/O pin (bank 4) |
| ピン 76 | GND — Ground |
| ピン 77 | I/O — User I/O pin (bank 5) |
| ピン 78 | I/O — User I/O pin (bank 5) |
| ピン 79 | I/O — User I/O pin (bank 5) |
| ピン 80 | I/O — User I/O pin (bank 5) |
| ピン 81 | I/O — User I/O pin (bank 5) |
| ピン 82 | I/O — User I/O pin (bank 5) |
| ピン 83 | I/O — User I/O pin (bank 5) |
| ピン 84 | GND — Ground |
| ピン 85 | I/O — User I/O pin (bank 5) |
| ピン 86 | I/O — User I/O pin (bank 5) |
| ピン 87 | I/O — User I/O pin (bank 5) |
| ピン 88 | I/O — User I/O pin (bank 5) |
| ピン 89 | I/O — User I/O pin (bank 5) |
| ピン 90 | I/O — User I/O pin (bank 5) |
| ピン 91 | I/O — User I/O pin (bank 5) |
| ピン 92 | GND — Ground |
| ピン 93 | I/O — User I/O pin (bank 6) |
| ピン 94 | I/O — User I/O pin (bank 6) |
| ピン 95 | I/O — User I/O pin (bank 6) |
| ピン 96 | I/O — User I/O pin (bank 6) |
| ピン 97 | I/O — User I/O pin (bank 6) |
| ピン 98 | I/O — User I/O pin (bank 6) |
| ピン 99 | I/O — User I/O pin (bank 6) |
| ピン 100 | I/O — User I/O pin (bank 6) |
| ピン 101 | GND — Ground |
| ピン 102 | I/O — User I/O pin (bank 6) |
| ピン 103 | I/O — User I/O pin (bank 6) |
| ピン 104 | I/O — User I/O pin (bank 6) |
| ピン 105 | I/O — User I/O pin (bank 6) |
| ピン 106 | I/O — User I/O pin (bank 6) |
| ピン 107 | I/O — User I/O pin (bank 6) |
| ピン 108 | GND — Ground |
| ピン 109 | I/O — User I/O pin (bank 7) |
| ピン 110 | I/O — User I/O pin (bank 7) |
| ピン 111 | I/O — User I/O pin (bank 7) |
| ピン 112 | I/O — User I/O pin (bank 7) |
| ピン 113 | I/O — User I/O pin (bank 7) |
| ピン 114 | I/O — User I/O pin (bank 7) |
| ピン 115 | I/O — User I/O pin (bank 7) |
| ピン 116 | I/O — User I/O pin (bank 7) |
| ピン 117 | GND — Ground |
| ピン 118 | I/O — User I/O pin (bank 7) |
| ピン 119 | I/O — User I/O pin (bank 7) |
| ピン 120 | I/O — User I/O pin (bank 7) |
| ピン 121 | I/O — User I/O pin (bank 7) |
| ピン 122 | I/O — User I/O pin (bank 7) |
| ピン 123 | I/O — User I/O pin (bank 7) |
| ピン 124 | I/O — User I/O pin (bank 7) |
| ピン 125 | GND — Ground |
| ピン 126 | I/O — User I/O pin (bank 8) |
| ピン 127 | I/O — User I/O pin (bank 8) |
| ピン 128 | I/O — User I/O pin (bank 8) |
| ピン 129 | I/O — User I/O pin (bank 8) |
| ピン 130 | I/O — User I/O pin (bank 8) |
| ピン 131 | I/O — User I/O pin (bank 8) |
| ピン 132 | I/O — User I/O pin (bank 8) |
| ピン 133 | I/O — User I/O pin (bank 8) |
| ピン 134 | GND — Ground |
| ピン 135 | I/O — User I/O pin (bank 8) |
| ピン 136 | I/O — User I/O pin (bank 8) |
| ピン 137 | I/O — User I/O pin (bank 8) |
| ピン 138 | I/O — User I/O pin (bank 8) |
| ピン 139 | I/O — User I/O pin (bank 8) |
| ピン 140 | I/O — User I/O pin (bank 8) |
| ピン 141 | I/O — User I/O pin (bank 8) |
| ピン 142 | OE2 — Global output enable 2 (active low) |
| ピン 143 | VCC — 3.3V core supply |
| ピン 144 | VCCIO — I/O supply (2.5V/3.3V/5V tolerant) |
主な用途
EPM7128AETC144-10 の用途: 7 件s: Bus Interface Bridging and Address Decoding, Industrial Control State Machines, Legacy Telecom Line Card Glue Logic, Peripheral I/O Expansion and GPIO Multiplexing, Military and Avionics Retrofit (Legacy), Test and Measurement Front-End Logic, Display Controller Interfacing.
Bus Interface Bridging and Address Decoding
The EPM7128AETC144-10 excels at bus-interface bridging in legacy industrial backplanes where a 3.3V/5V-tolerant CPLD must decode addresses, generate chip selects, and arbitrate interrupts across a 16- or 32-bit bus. Its 128 macrocells and 36 user I/Os comfortably absorb full 8-bit chip-select decoders with one-hot or binary encoding, plus wait-state insertion logic, while the 10 ns tPD guarantees sub-bus-clock timing closure. Designers typically wire OE1 and OE2 as global output enables tied to read/write strobes, and use GCLK1/GCLK2 for synchronous handshake logic. Unlike an FPGA, the EEPROM-based MAX 7000A boots in microseconds with no external PROM, making the part ideal for cold-start deterministic systems.
おすすめ
Industrial Control State Machines
The EPM7128AETC144-10 is widely deployed in PLC and motor-control boards implementing deterministic state machines for valve sequencing, conveyor indexing, and safety interlocks. The 128 macrocells comfortably encode 8- to 16-state Moore or Mealy machines with parallel output decoding, while the 10 ns combinatorial delay keeps state transitions well within typical 1 ms scan-cycle budgets. The MAX 7000A EEPROM fabric means the controller boots into a known state at power-on with no configuration flash, a property required by IEC 61508 SIL-1/SIL-2 systems. The commercial 0C to +70C temperature range covers most factory-floor enclosures, and the JTAG interface lets engineers iterate on state tables via Quartus Prime during commissioning.
おすすめ
Legacy Telecom Line Card Glue Logic
In T1/E1 and DSLAM line-card designs, the EPM7128AETC144-10 serves as glue logic between framers, LIUs (line interface units), and the central switching ASIC. Its 5V-tolerant I/Os connect directly to legacy bipolar ECL/TTL framers, while the 3.3V core talks to modern CMOS ASICs, eliminating level translators. With 36 user I/Os the device can manage HDLC channel mapping, framer alarm aggregation, and per-port loopback switching on a single chip. The 10 ns tPD ensures that per-port status registers are latched before the next 8 kHz frame pulse. The MAX 7000A's non-volatile configuration also keeps the line card in a safe default state during firmware updates.
おすすめ
Peripheral I/O Expansion and GPIO Multiplexing
The EPM7128AETC144-10 is a strong choice for I/O expansion where an SoC lacks sufficient GPIOs for LCD, keypad, and peripheral multiplexing. With 36 user I/Os and 5V tolerance, the device can directly drive character LCDs, scan 4x4 keypads, and arbitrate SPI/I2C/UART buses without external level shifters. The EEPROM fabric lets designers iterate on pin maps during prototype without re-flashing an MCU. The 10 ns combinatorial delay ensures glitch-free mux switching, and the JTAG interface supports boundary-scan (IEEE 1149.1) for board-level interconnect test, dramatically simplifying in-circuit test of dense mixed-signal PCBs.
おすすめ
Military and Avionics Retrofit (Legacy)
The EPM7128AETC144-10 remains in long-life avionics retrofit programs where the MAX 7000A is already qualified to DO-254 Design Assurance Level C. Its deterministic 10 ns timing, EEPROM non-volatility, and proven flight heritage make it suitable for cockpit display multiplexing, navigation sensor arbitration, and redundant bus voting. The 144-TQFP package withstands the standard aerospace thermal cycling profile when paired with proper underfill. Note that for new aerospace programs designers should evaluate MAX V or radiation-tolerant FPGAs, as the original 7000A family is NRND and not recommended for new safety-critical designs.
おすすめ
Test and Measurement Front-End Logic
In bench-top oscilloscopes, logic analyzers, and protocol testers, the EPM7128AETC144-10 implements front-end channel switching, range relay control, and trigger-arm logic. The 5V-tolerant I/Os drive legacy analog switches directly, while the 3.3V core interfaces to modern ADC front-ends. The 128 macrocells absorb full trigger sequencers with pre-/post-/holdoff counters, and the 10 ns tPD ensures trigger-to-acquisition latency stays below one ADC sample clock. The EEPROM fabric allows trigger logic to be customized per product variant (e.g., UART vs SPI vs I2C triggering) without changing the firmware image.
おすすめ
Display Controller Interfacing
The EPM7128AETC144-10 bridges TFT LCD panels to legacy 8/16-bit microcontroller buses by generating WR/RD strobes, converting pixel data timing, and providing backlight PWM control. The 36 user I/Os comfortably handle 16-bit data plus control signals, while the EEPROM fabric stores per-panel timing parameters in logic without external EEPROM. The 10 ns tPD keeps pixel-clock-to-data setup margin healthy even at 25 MHz WVGA timings. The 5V-tolerant I/Os allow direct connection to industrial 5V MCU buses, eliminating level shifters in cost-sensitive HMI designs.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: EPM7128AETC144-10 — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | EPM7128AETC144-10N | EPM7128AETC144-7 | EPM7128AETC144-15 | EPM7128AETI144-7 | EPM7128AETC100-10 |
|---|---|---|---|---|---|---|
| Brand | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) |
| Package | 144-pin TQFP | 144-pin TQFP - same | 144-pin TQFP - same | 144-pin TQFP - same | 144-pin TQFP - same | 100-pin TQFP - different |
| Macrocells | 128 | 128 | 128 | 128 | 128 | 128 |
| Pin-to-pin Delay (tPD) | 10 ns | 10 ns | 7 ns (faster) | 15 ns (slower) | 7 ns (faster) | 10 ns |
| Maximum Internal Frequency | 98 MHz | 98 MHz | 125 MHz | 83 MHz | 125 MHz | 98 MHz |
| Maximum User I/Os | 36 | 36 | 36 | 36 | 36 | 84 (different package) |
| Temperature Grade | Commercial (0C to +70C) | Commercial (0C to +70C) | Commercial (0C to +70C) | Commercial (0C to +70C) | Industrial (-40C to +85C) | Commercial (0C to +70C) |
| Lead-free Plating | Standard (SnPb) | Pb-free (NiPdAu) | Standard (SnPb) | Standard (SnPb) | Standard (SnPb) | Standard (SnPb) |
主な差別化要因
- Drop-in 144-TQFP compatibility with -7 and -15 speed grades （vs EPM7128AETC144-7 / EPM7128AETC144-15)
- Non-volatile EEPROM fabric, instant-on at power-up （vs SRAM-based FPGAs (e.g. Cyclone, Spartan))
- 5V-tolerant I/Os on a 3.3V core （vs Pure 3.3V CPLDs (e.g. MAX II))
設計ノート
Estimated: The MAX 7000A core draws approximately 10 mA quiescent plus dynamic current during toggling; at 100 MHz toggle rate with 36 I/Os switching 5 pF loads, expect 30-50 mA additional. Provide a 100 uF bulk capacitor plus 0.1 uF decoupling within 5 mm of each VCC/VCCIO pin pair. Although the core runs on 3.3V, the I/O banks tolerate 2.5V/3.3V/5V inputs when VCCIO is set accordingly, allowing mixed-voltage buses without level shifters.
The 144-pin TQFP has a 0.5 mm pitch; route signals on the top layer with 0.2 mm trace/space and use a 4-layer stack-up with dedicated ground/power planes. Keep JTAG traces (TCK/TMS/TDI/TDO) short (<50 mm) and series-terminate TCK with 33 ohm to suppress ringing on the 1149.1 boundary-scan clock. Expose all four JTAG signals on a 2x5 header to support ByteBlaster MV programming in-circuit.
Always specify the 'N' suffix (EPM7128AETC144-10N) for new designs to ensure Pb-free / RoHS-compliant assembly per JEDEC J-STD-020 MSL3. Do not confuse the EPM7128AETC144-10 with the EPM7128AETC100-10 (different package, fewer user I/Os even though macrocells match) - they are NOT drop-in compatible. When migrating to MAX II (EPM570), note that the MAX II has a different JTAG chain ordering and requires Quartus Prime re-programming.
For high-speed outputs (>50 MHz toggle), place 22 ohm series resistors near the CPLD pin to dampen transmission-line reflections into the 50 ohm micro-strip. Slew-rate control is available per pin via Quartus Prime (slow slew option) and should be enabled on long board traces to reduce EMI. Global clocks GCLK1/GCLK2 should be driven from a low-skew clock buffer; do not use regular I/O pins for clock distribution above 50 MHz.
コンプライアンス情報
Standard EPM7128AETC144-10 has SnPb lead finish and is RoHS non-compliant; choose the -10N suffix variant for Pb-free RoHS-compliant assembly. The MAX 7000A family is not AEC-Q100 qualified (automotive designers should evaluate automotive-grade CPLDs). REACH compliance confirmed by Intel product declaration.
